block1.map.qmsg

暑假时参加电子设计大赛曾经用EDA开发实现液晶显示TJUCI学校名的一个小程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 09 14:51:36 2005 " "Info: Processing started: Tue Aug 09 14:51:36 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Block1 -c Block1 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Block1 -c Block1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock2500.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock2500.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock2500-arc " "Info: Found design unit 1: clock2500-arc" {  } { { "F:/ledTJUCI/clock2500.vhd" "clock2500-arc" "" { Text "F:/ledTJUCI/clock2500.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clock2500 " "Info: Found entity 1: clock2500" {  } { { "F:/ledTJUCI/clock2500.vhd" "clock2500" "" { Text "F:/ledTJUCI/clock2500.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "YIMAQI.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file YIMAQI.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 YIMAQI-arc_YIMAQI " "Info: Found design unit 1: YIMAQI-arc_YIMAQI" {  } { { "F:/ledTJUCI/YIMAQI.vhd" "YIMAQI-arc_YIMAQI" "" { Text "F:/ledTJUCI/YIMAQI.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 YIMAQI " "Info: Found entity 1: YIMAQI" {  } { { "F:/ledTJUCI/YIMAQI.vhd" "YIMAQI" "" { Text "F:/ledTJUCI/YIMAQI.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND1.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file AND1.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND1-ARC_AND1 " "Info: Found design unit 1: AND1-ARC_AND1" {  } { { "F:/ledTJUCI/AND1.VHD" "AND1-ARC_AND1" "" { Text "F:/ledTJUCI/AND1.VHD" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 AND1 " "Info: Found entity 1: AND1" {  } { { "F:/ledTJUCI/AND1.VHD" "AND1" "" { Text "F:/ledTJUCI/AND1.VHD" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ANDL.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file ANDL.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ANDL-ARC_ANDL " "Info: Found design unit 1: ANDL-ARC_ANDL" {  } { { "F:/ledTJUCI/ANDL.VHD" "ANDL-ARC_ANDL" "" { Text "F:/ledTJUCI/ANDL.VHD" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ANDL " "Info: Found entity 1: ANDL" {  } { { "F:/ledTJUCI/ANDL.VHD" "ANDL" "" { Text "F:/ledTJUCI/ANDL.VHD" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ROM.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file ROM.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ROM-arc_ROM " "Info: Found design unit 1: ROM-arc_ROM" {  } { { "F:/ledTJUCI/ROM.VHD" "ROM-arc_ROM" "" { Text "F:/ledTJUCI/ROM.VHD" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Info: Found entity 1: ROM" {  } { { "F:/ledTJUCI/ROM.VHD" "ROM" "" { Text "F:/ledTJUCI/ROM.VHD" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "F:/ledTJUCI/Block1.bdf" "Block1" "" { Schematic "F:/ledTJUCI/Block1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DELED.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DELED.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DELED-arc_DELED " "Info: Found design unit 1: DELED-arc_DELED" {  } { { "F:/ledTJUCI/DELED.vhd" "DELED-arc_DELED" "" { Text "F:/ledTJUCI/DELED.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DELED " "Info: Found entity 1: DELED" {  } { { "F:/ledTJUCI/DELED.vhd" "DELED" "" { Text "F:/ledTJUCI/DELED.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock800.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock800.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock800-arc " "Info: Found design unit 1: clock800-arc" {  } { { "F:/ledTJUCI/clock800.vhd" "clock800-arc" "" { Text "F:/ledTJUCI/clock800.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 clock800 " "Info: Found entity 1: clock800" {  } { { "F:/ledTJUCI/clock800.vhd" "clock800" "" { Text "F:/ledTJUCI/clock800.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cr ROM.VHD(15) " "Warning: VHDL Process Statement warning at ROM.VHD(15): signal cr is in statement, but is not in sensitivity list" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 15 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ROM.VHD(154) " "Info: VHDL Case Statement information at ROM.VHD(154): OTHERS choice is never selected" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 154 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dout ROM.VHD(13) " "Warning: VHDL Process Statement warning at ROM.VHD(13): signal or variable dout may not be assigned a new value in every possible path through the Process Statement. Signal or variable dout holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d1in DELED.vhd(16) " "Warning: VHDL Process Statement warning at DELED.vhd(16): signal d1in is in statement, but is not in sensitivity list" {  } { { "F:/ledTJUCI/DELED.vhd" "" "" { Text "F:/ledTJUCI/DELED.vhd" 16 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "DELED.vhd(25) " "Info: VHDL Case Statement information at DELED.vhd(25): OTHERS choice is never selected" {  } { { "F:/ledTJUCI/DELED.vhd" "" "" { Text "F:/ledTJUCI/DELED.vhd" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d2in YIMAQI.vhd(14) " "Warning: VHDL Process Statement warning at YIMAQI.vhd(14): signal d2in is in statement, but is not in sensitivity list" {  } { { "F:/led1/YIMAQI.vhd" "" "" { Text "F:/led1/YIMAQI.vhd" 14 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "YIMAQI.vhd(23) " "Info: VHDL Case Statement information at YIMAQI.vhd(23): OTHERS choice is never selected" {  } { { "F:/led1/YIMAQI.vhd" "" "" { Text "F:/led1/YIMAQI.vhd" 23 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "ANDL:inst1\|dou\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: ANDL:inst1\|dou\[0\]~4" {  } { { "f:/led/ANDL.VHD" "" "dou\[0\]~4" { Text "f:/led/ANDL.VHD" 18 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "alt_counter_f10ke" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "d:/altera/quartus41/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "d:/altera/quartus41/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus41/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "d:/altera/quartus41/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "d:/altera/quartus41/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "16 " "Info: Ignored 16 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "16 " "Info: Ignored 16 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "293 " "Info: Implemented 293 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "35 " "Info: Implemented 35 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "255 " "Info: Implemented 255 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 09 14:51:41 2005 " "Info: Processing ended: Tue Aug 09 14:51:41 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}