block2.tan.qmsg

暑假时参加电子设计大赛曾经用EDA开发实现液晶显示TJUCI学校名的一个小程序

{ "Info" "ITDB_FULL_TPD_RESULT" "CR L1 17.200 ns Longest " "Info: Longest tpd from source pin CR to destination pin L1 is 17.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CR 1 PIN PIN_84 48 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 48; PIN Node = 'CR'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { CR } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 200 -72 96 216 "CR" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(2.300 ns) 7.600 ns ROM:inst2\|dout\[1\]~1347 2 COMB LC8_C15 2 " "Info: 2: + IC(2.500 ns) + CELL(2.300 ns) = 7.600 ns; Loc. = LC8_C15; Fanout = 2; COMB Node = 'ROM:inst2\|dout\[1\]~1347'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "4.800 ns" { CR ROM:inst2|dout[1]~1347 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 10.500 ns ROM:inst2\|dout\[1\]~1308 3 COMB LOOP LC7_C15 3 " "Info: 3: + IC(0.000 ns) + CELL(2.900 ns) = 10.500 ns; Loc. = LC7_C15; Fanout = 3; COMB LOOP Node = 'ROM:inst2\|dout\[1\]~1308'" { { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[1\]~1346 LC6_C15 " "Info: Loc. = LC6_C15; Node ROM:inst2\|dout\[1\]~1346" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[1]~1346 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[1\]~1308 LC7_C15 " "Info: Loc. = LC7_C15; Node ROM:inst2\|dout\[1\]~1308" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[1]~1308 } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[1]~1346 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[1]~1308 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.900 ns" { ROM:inst2|dout[1]~1347 ROM:inst2|dout[1]~1308 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 17.200 ns L1 4 PIN PIN_58 0 " "Info: 4: + IC(1.600 ns) + CELL(5.100 ns) = 17.200 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'L1'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "6.700 ns" { ROM:inst2|dout[1]~1308 L1 } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 336 616 792 352 "L1" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.100 ns 76.16 % " "Info: Total cell delay = 13.100 ns ( 76.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.100 ns 23.84 % " "Info: Total interconnect delay = 4.100 ns ( 23.84 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "17.200 ns" { CR ROM:inst2|dout[1]~1347 ROM:inst2|dout[1]~1308 L1 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CKDSP SEL3 ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 12.500 ns register " "Info: Minimum tco from clock CKDSP to destination pin SEL3 through register ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] is 12.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CKDSP source 5.300 ns + Shortest register " "Info: + Shortest clock path from clock CKDSP to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CKDSP 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'CKDSP'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { CKDSP } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 248 -56 112 264 "CKDSP" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_B4 102 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B4; Fanout = 102; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_B4 102 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B4; Fanout = 102; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 6.100 ns SEL3 2 PIN PIN_8 0 " "Info: 2: + IC(1.000 ns) + CELL(5.100 ns) = 6.100 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'SEL3'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "6.100 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] SEL3 } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 448 520 696 464 "SEL3" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns 83.61 % " "Info: Total cell delay = 5.100 ns ( 83.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 16.39 % " "Info: Total interconnect delay = 1.000 ns ( 16.39 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "6.100 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] SEL3 } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "6.100 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] SEL3 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CR L14 12.900 ns Shortest " "Info: Shortest tpd from source pin CR to destination pin L14 is 12.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CR 1 PIN PIN_84 48 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 48; PIN Node = 'CR'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { CR } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 200 -72 96 216 "CR" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 6.800 ns ROM:inst2\|dout\[14\]~1295 2 COMB LOOP LC2_B21 3 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 6.800 ns; Loc. = LC2_B21; Fanout = 3; COMB LOOP Node = 'ROM:inst2\|dout\[14\]~1295'" { { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[14\]~1311 LC7_B21 " "Info: Loc. = LC7_B21; Node ROM:inst2\|dout\[14\]~1311" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[14]~1311 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[14\]~1295 LC2_B21 " "Info: Loc. = LC2_B21; Node ROM:inst2\|dout\[14\]~1295" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[14]~1295 } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[14]~1311 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[14]~1295 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "4.000 ns" { CR ROM:inst2|dout[14]~1295 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 12.900 ns L14 3 PIN PIN_54 0 " "Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 12.900 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'L14'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "6.100 ns" { ROM:inst2|dout[14]~1295 L14 } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 128 616 792 144 "L14" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.900 ns 92.25 % " "Info: Total cell delay = 11.900 ns ( 92.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 7.75 % " "Info: Total interconnect delay = 1.000 ns ( 7.75 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "12.900 ns" { CR ROM:inst2|dout[14]~1295 L14 } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 09 08:43:09 2005 " "Info: Processing ended: Tue Aug 09 08:43:09 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}