📄 block2.tan.qmsg

📁 暑假时参加电子设计大赛曾经用EDA开发实现液晶显示TJUCI学校名的一个小程序
💻 QMSG
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{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[12\]~1297 " "Info: Node ROM:inst2\|dout\[12\]~1297" {  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[12\]~1317 " "Info: Node ROM:inst2\|dout\[12\]~1317" {  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0}  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[13\]~1296 " "Info: Node ROM:inst2\|dout\[13\]~1296" {  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[13\]~1314 " "Info: Node ROM:inst2\|dout\[13\]~1314" {  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0}  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[14\]~1295 " "Info: Node ROM:inst2\|dout\[14\]~1295" {  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[14\]~1311 " "Info: Node ROM:inst2\|dout\[14\]~1311" {  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0}  } { { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "HZSEL " "Info: Assuming node HZSEL is an undefined clock" {  } { { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 128 -56 112 144 "HZSEL" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "HZSEL" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CKDSP " "Info: Assuming node CKDSP is an undefined clock" {  } { { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 248 -56 112 264 "CKDSP" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CKDSP" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "HZSEL register AND1:inst\|dou\[0\] register AND1:inst\|dou\[1\] 119.05 MHz 8.4 ns Internal " "Info: Clock HZSEL has Internal fmax of 119.05 MHz between source register AND1:inst\|dou\[0\] and destination register AND1:inst\|dou\[1\] (period= 8.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest register register " "Info: + Longest register to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AND1:inst\|dou\[0\] 1 REG LC1_B7 85 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B7; Fanout = 85; REG Node = 'AND1:inst\|dou\[0\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { AND1:inst|dou[0] } "NODE_NAME" } } } { "f:/led1/AND1.VHD" "" "" { Text "f:/led1/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.700 ns) 4.800 ns AND1:inst\|dou\[1\] 2 REG LC3_A12 76 " "Info: 2: + IC(3.100 ns) + CELL(1.700 ns) = 4.800 ns; Loc. = LC3_A12; Fanout = 76; REG Node = 'AND1:inst\|dou\[1\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "4.800 ns" { AND1:inst|dou[0] AND1:inst|dou[1] } "NODE_NAME" } } } { "f:/led1/AND1.VHD" "" "" { Text "f:/led1/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 35.42 % " "Info: Total cell delay = 1.700 ns ( 35.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns 64.58 % " "Info: Total interconnect delay = 3.100 ns ( 64.58 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "4.800 ns" { AND1:inst|dou[0] AND1:inst|dou[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "HZSEL destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock HZSEL to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns HZSEL 1 CLK PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'HZSEL'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { HZSEL } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 128 -56 112 144 "HZSEL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns AND1:inst\|dou\[1\] 2 REG LC3_A12 76 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_A12; Fanout = 76; REG Node = 'AND1:inst\|dou\[1\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { HZSEL AND1:inst|dou[1] } "NODE_NAME" } } } { "f:/led1/AND1.VHD" "" "" { Text "f:/led1/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { HZSEL AND1:inst|dou[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "HZSEL source 5.300 ns - Longest register " "Info: - Longest clock path from clock HZSEL to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns HZSEL 1 CLK PIN_1 3 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 3; CLK Node = 'HZSEL'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { HZSEL } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 128 -56 112 144 "HZSEL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns AND1:inst\|dou\[0\] 2 REG LC1_B7 85 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B7; Fanout = 85; REG Node = 'AND1:inst\|dou\[0\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { HZSEL AND1:inst|dou[0] } "NODE_NAME" } } } { "f:/led1/AND1.VHD" "" "" { Text "f:/led1/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { HZSEL AND1:inst|dou[0] } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { HZSEL AND1:inst|dou[1] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { HZSEL AND1:inst|dou[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "f:/led1/AND1.VHD" "" "" { Text "f:/led1/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "f:/led1/AND1.VHD" "" "" { Text "f:/led1/AND1.VHD" 16 -1 0 } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "4.800 ns" { AND1:inst|dou[0] AND1:inst|dou[1] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { HZSEL AND1:inst|dou[1] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { HZSEL AND1:inst|dou[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CKDSP register register ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 125.0 MHz Internal " "Info: Clock CKDSP Internal fmax is restricted to 125.0 MHz between source register ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] and destination register ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.500 ns + Longest register register " "Info: + Longest register to register delay is 2.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_B4 116 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B4; Fanout = 116; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT 2 COMB LC1_B4 2 " "Info: 2: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = LC1_B4; Fanout = 2; COMB Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "1.200 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 1.500 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT 3 COMB LC2_B4 3 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.500 ns; Loc. = LC2_B4; Fanout = 3; COMB Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "0.300 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 1.800 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT 4 COMB LC3_B4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_B4; Fanout = 1; COMB Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "0.300 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 2.500 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 5 REG LC4_B4 102 " "Info: 5: + IC(0.000 ns) + CELL(0.700 ns) = 2.500 ns; Loc. = LC4_B4; Fanout = 102; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "0.700 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 100.00 % " "Info: Total cell delay = 2.500 ns ( 100.00 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CKDSP destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock CKDSP to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CKDSP 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'CKDSP'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { CKDSP } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 248 -56 112 264 "CKDSP" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_B4 102 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B4; Fanout = 102; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CKDSP source 5.300 ns - Longest register " "Info: - Longest clock path from clock CKDSP to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CKDSP 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'CKDSP'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { CKDSP } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 248 -56 112 264 "CKDSP" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B4 116 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B4; Fanout = 116; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CKDSP L6 ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 39.400 ns register " "Info: tco from clock CKDSP to destination pin L6 through register ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] is 39.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CKDSP source 5.300 ns + Longest register " "Info: + Longest clock path from clock CKDSP to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CKDSP 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'CKDSP'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { CKDSP } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 248 -56 112 264 "CKDSP" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC2_B4 107 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B4; Fanout = 107; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.500 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "33.000 ns + Longest register pin " "Info: + Longest register to pin delay is 33.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 1 REG LC2_B4 107 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B4; Fanout = 107; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.800 ns) + CELL(2.300 ns) 10.100 ns ROM:inst2\|Mux~354 2 COMB LC4_C22 1 " "Info: 2: + IC(7.800 ns) + CELL(2.300 ns) = 10.100 ns; Loc. = LC4_C22; Fanout = 1; COMB Node = 'ROM:inst2\|Mux~354'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "10.100 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ROM:inst2|Mux~354 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.300 ns) 15.000 ns ROM:inst2\|Mux~622 3 COMB LC2_C14 1 " "Info: 3: + IC(2.600 ns) + CELL(2.300 ns) = 15.000 ns; Loc. = LC2_C14; Fanout = 1; COMB Node = 'ROM:inst2\|Mux~622'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "4.900 ns" { ROM:inst2|Mux~354 ROM:inst2|Mux~622 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.300 ns) 20.500 ns ROM:inst2\|Mux~623 4 COMB LC5_A17 3 " "Info: 4: + IC(3.200 ns) + CELL(2.300 ns) = 20.500 ns; Loc. = LC5_A17; Fanout = 3; COMB Node = 'ROM:inst2\|Mux~623'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.500 ns" { ROM:inst2|Mux~622 ROM:inst2|Mux~623 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 23.400 ns ROM:inst2\|dout\[6\]~1334 5 COMB LC7_A17 2 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 23.400 ns; Loc. = LC7_A17; Fanout = 2; COMB Node = 'ROM:inst2\|dout\[6\]~1334'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.900 ns" { ROM:inst2|Mux~623 ROM:inst2|dout[6]~1334 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 26.300 ns ROM:inst2\|dout\[6\]~1303 6 COMB LOOP LC8_A17 3 " "Info: 6: + IC(0.000 ns) + CELL(2.900 ns) = 26.300 ns; Loc. = LC8_A17; Fanout = 3; COMB LOOP Node = 'ROM:inst2\|dout\[6\]~1303'" { { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[6\]~1333 LC6_A17 " "Info: Loc. = LC6_A17; Node ROM:inst2\|dout\[6\]~1333" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[6]~1333 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[6\]~1303 LC8_A17 " "Info: Loc. = LC8_A17; Node ROM:inst2\|dout\[6\]~1303" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[6]~1303 } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[6]~1333 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[6]~1303 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "2.900 ns" { ROM:inst2|dout[6]~1334 ROM:inst2|dout[6]~1303 } "NODE_NAME" } } } { "f:/led1/ROM.VHD" "" "" { Text "f:/led1/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 33.000 ns L6 7 PIN PIN_69 0 " "Info: 7: + IC(1.600 ns) + CELL(5.100 ns) = 33.000 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'L6'" {  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "6.700 ns" { ROM:inst2|dout[6]~1303 L6 } "NODE_NAME" } } } { "f:/led1/Block2.bdf" "" "" { Schematic "f:/led1/Block2.bdf" { { 256 616 792 272 "L6" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.200 ns 52.12 % " "Info: Total cell delay = 17.200 ns ( 52.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.800 ns 47.88 % " "Info: Total interconnect delay = 15.800 ns ( 47.88 % )" {  } {  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "33.000 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ROM:inst2|Mux~354 ROM:inst2|Mux~622 ROM:inst2|Mux~623 ROM:inst2|dout[6]~1334 ROM:inst2|dout[6]~1303 L6 } "NODE_NAME" } } }  } 0}  } { { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "5.300 ns" { CKDSP ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } } { "f:/led1/db/Block2_cmp.qrpt" "" "" { Report "f:/led1/db/Block2_cmp.qrpt" Compiler "Block2" "UNKNOWN" "V1" "f:/led1/db/Block2.quartus_db" { Floorplan "" "" "33.000 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ROM:inst2|Mux~354 ROM:inst2|Mux~622 ROM:inst2|Mux~623 ROM:inst2|dout[6]~1334 ROM:inst2|dout[6]~1303 L6 } "NODE_NAME" } } }  } 0}
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