block1.tan.qmsg

暑假时参加电子设计大赛曾经用EDA开发实现液晶显示TJUCI学校名的一个小程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin L11 ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 42.500 ns register " "Info: tco from clock clkin to destination pin L11 through register ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] is 42.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 11.000 ns + Longest register " "Info: + Longest clock path from clock clkin to source register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_1 11 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 11; CLK Node = 'clkin'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { clkin } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 248 -240 -72 264 "clkin" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clock800:inst4\|clkout5k 2 REG LC1_B14 5 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B14; Fanout = 5; REG Node = 'clock800:inst4\|clkout5k'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "3.600 ns" { clkin clock800:inst4|clkout5k } "NODE_NAME" } } } { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 3 REG LC5_A3 96 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC5_A3; Fanout = 96; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "4.600 ns" { clock800:inst4|clkout5k ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.45 % " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 64.55 % " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "11.000 ns" { clkin clock800:inst4|clkout5k ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "30.400 ns + Longest register pin " "Info: + Longest register to pin delay is 30.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC5_A3 96 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A3; Fanout = 96; REG Node = 'ANDL:inst1\|lpm_counter:dou_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.100 ns) + CELL(2.300 ns) 7.400 ns ROM:inst2\|Mux~262 2 COMB LC5_C12 1 " "Info: 2: + IC(5.100 ns) + CELL(2.300 ns) = 7.400 ns; Loc. = LC5_C12; Fanout = 1; COMB Node = 'ROM:inst2\|Mux~262'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ROM:inst2|Mux~262 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(2.300 ns) 13.000 ns ROM:inst2\|Mux~573 3 COMB LC1_A2 1 " "Info: 3: + IC(3.300 ns) + CELL(2.300 ns) = 13.000 ns; Loc. = LC1_A2; Fanout = 1; COMB Node = 'ROM:inst2\|Mux~573'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "5.600 ns" { ROM:inst2|Mux~262 ROM:inst2|Mux~573 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.300 ns) 17.900 ns ROM:inst2\|Mux~574 4 COMB LC6_A6 3 " "Info: 4: + IC(2.600 ns) + CELL(2.300 ns) = 17.900 ns; Loc. = LC6_A6; Fanout = 3; COMB Node = 'ROM:inst2\|Mux~574'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "4.900 ns" { ROM:inst2|Mux~573 ROM:inst2|Mux~574 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 20.800 ns ROM:inst2\|dout\[11\]~1523 5 COMB LC8_A6 2 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 20.800 ns; Loc. = LC8_A6; Fanout = 2; COMB Node = 'ROM:inst2\|dout\[11\]~1523'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.900 ns" { ROM:inst2|Mux~574 ROM:inst2|dout[11]~1523 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 23.700 ns ROM:inst2\|dout\[11\]~1504 6 COMB LOOP LC3_A6 3 " "Info: 6: + IC(0.000 ns) + CELL(2.900 ns) = 23.700 ns; Loc. = LC3_A6; Fanout = 3; COMB LOOP Node = 'ROM:inst2\|dout\[11\]~1504'" { { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[11\]~1522 LC7_A6 " "Info: Loc. = LC7_A6; Node ROM:inst2\|dout\[11\]~1522" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[11]~1522 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[11\]~1504 LC3_A6 " "Info: Loc. = LC3_A6; Node ROM:inst2\|dout\[11\]~1504" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[11]~1504 } "NODE_NAME" } } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[11]~1522 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[11]~1504 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.900 ns" { ROM:inst2|dout[11]~1523 ROM:inst2|dout[11]~1504 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 30.400 ns L11 7 PIN PIN_17 0 " "Info: 7: + IC(1.600 ns) + CELL(5.100 ns) = 30.400 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'L11'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "6.700 ns" { ROM:inst2|dout[11]~1504 L11 } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 176 616 792 192 "L11" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.200 ns 56.58 % " "Info: Total cell delay = 17.200 ns ( 56.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.200 ns 43.42 % " "Info: Total interconnect delay = 13.200 ns ( 43.42 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "30.400 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ROM:inst2|Mux~262 ROM:inst2|Mux~573 ROM:inst2|Mux~574 ROM:inst2|dout[11]~1523 ROM:inst2|dout[11]~1504 L11 } "NODE_NAME" } } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "11.000 ns" { clkin clock800:inst4|clkout5k ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "30.400 ns" { ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ROM:inst2|Mux~262 ROM:inst2|Mux~573 ROM:inst2|Mux~574 ROM:inst2|dout[11]~1523 ROM:inst2|dout[11]~1504 L11 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CR L4 25.300 ns Longest " "Info: Longest tpd from source pin CR to destination pin L4 is 25.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns CR 1 PIN PIN_62 38 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_62; Fanout = 38; PIN Node = 'CR'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { CR } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 200 -136 32 216 "CR" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(9.000 ns) + CELL(2.300 ns) 14.800 ns ROM:inst2\|dout\[4\]~1536 2 COMB LC8_A2 2 " "Info: 2: + IC(9.000 ns) + CELL(2.300 ns) = 14.800 ns; Loc. = LC8_A2; Fanout = 2; COMB Node = 'ROM:inst2\|dout\[4\]~1536'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "11.300 ns" { CR ROM:inst2|dout[4]~1536 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 17.700 ns ROM:inst2\|dout\[4\]~1511 3 COMB LOOP LC6_A2 3 " "Info: 3: + IC(0.000 ns) + CELL(2.900 ns) = 17.700 ns; Loc. = LC6_A2; Fanout = 3; COMB LOOP Node = 'ROM:inst2\|dout\[4\]~1511'" { { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[4\]~1535 LC7_A2 " "Info: Loc. = LC7_A2; Node ROM:inst2\|dout\[4\]~1535" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[4]~1535 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "ROM:inst2\|dout\[4\]~1511 LC6_A2 " "Info: Loc. = LC6_A2; Node ROM:inst2\|dout\[4\]~1511" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[4]~1511 } "NODE_NAME" } } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[4]~1535 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { ROM:inst2|dout[4]~1511 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.900 ns" { ROM:inst2|dout[4]~1536 ROM:inst2|dout[4]~1511 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(5.100 ns) 25.300 ns L4 4 PIN PIN_24 0 " "Info: 4: + IC(2.500 ns) + CELL(5.100 ns) = 25.300 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'L4'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.600 ns" { ROM:inst2|dout[4]~1511 L4 } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 288 616 792 304 "L4" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.800 ns 54.55 % " "Info: Total cell delay = 13.800 ns ( 54.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.500 ns 45.45 % " "Info: Total interconnect delay = 11.500 ns ( 45.45 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "25.300 ns" { CR ROM:inst2|dout[4]~1536 ROM:inst2|dout[4]~1511 L4 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "hzsel LED\[5\] AND1:inst\|dou\[1\] 17.000 ns register " "Info: Minimum tco from clock hzsel to destination pin LED\[5\] through register AND1:inst\|dou\[1\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "hzsel source 7.400 ns + Shortest register " "Info: + Shortest clock path from clock hzsel to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns hzsel 1 CLK PIN_52 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_52; Fanout = 3; CLK Node = 'hzsel'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { hzsel } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 128 -144 24 144 "hzsel" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 7.400 ns AND1:inst\|dou\[1\] 2 REG LC6_B11 68 " "Info: 2: + IC(3.900 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC6_B11; Fanout = 68; REG Node = 'AND1:inst\|dou\[1\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "3.900 ns" { hzsel AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 47.30 % " "Info: Total cell delay = 3.500 ns ( 47.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 52.70 % " "Info: Total interconnect delay = 3.900 ns ( 52.70 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Shortest register pin " "Info: + Shortest register to pin delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AND1:inst\|dou\[1\] 1 REG LC6_B11 68 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_B11; Fanout = 68; REG Node = 'AND1:inst\|dou\[1\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 2.400 ns YIMAQI:inst3\|LED\[0\]~61 2 COMB LC1_B11 1 " "Info: 2: + IC(0.600 ns) + CELL(1.800 ns) = 2.400 ns; Loc. = LC1_B11; Fanout = 1; COMB Node = 'YIMAQI:inst3\|LED\[0\]~61'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.400 ns" { AND1:inst|dou[1] YIMAQI:inst3|LED[0]~61 } "NODE_NAME" } } } { "F:/led1/YIMAQI.vhd" "" "" { Text "F:/led1/YIMAQI.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 8.500 ns LED\[5\] 3 PIN PIN_39 0 " "Info: 3: + IC(1.000 ns) + CELL(5.100 ns) = 8.500 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'LED\[5\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "6.100 ns" { YIMAQI:inst3|LED[0]~61 LED[5] } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 576 656 832 592 "LED\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns 81.18 % " "Info: Total cell delay = 6.900 ns ( 81.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 18.82 % " "Info: Total interconnect delay = 1.600 ns ( 18.82 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "8.500 ns" { AND1:inst|dou[1] YIMAQI:inst3|LED[0]~61 LED[5] } "NODE_NAME" } } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "8.500 ns" { AND1:inst|dou[1] YIMAQI:inst3|LED[0]~61 LED[5] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CR L15 15.600 ns Shortest " "Info: Shortest tpd from source pin CR to destination pin L15 is 15.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns CR 1 PIN PIN_62 38 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_62; Fanout = 38; PIN Node = 'CR'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { CR } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 200 -136 32 216 "CR" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(2.300 ns) 9.600 ns ROM:inst2\|dout\[15\]~1500 2 COMB LC1_C15 2 " "Info: 2: + IC(3.800 ns) + CELL(2.300 ns) = 9.600 ns; Loc. = LC1_C15; Fanout = 2; COMB Node = 'ROM:inst2\|dout\[15\]~1500'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "6.100 ns" { CR ROM:inst2|dout[15]~1500 } "NODE_NAME" } } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(5.100 ns) 15.600 ns L15 3 PIN PIN_49 0 " "Info: 3: + IC(0.900 ns) + CELL(5.100 ns) = 15.600 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'L15'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "6.000 ns" { ROM:inst2|dout[15]~1500 L15 } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 112 616 792 128 "L15" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.900 ns 69.87 % " "Info: Total cell delay = 10.900 ns ( 69.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 30.13 % " "Info: Total interconnect delay = 4.700 ns ( 30.13 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "15.600 ns" { CR ROM:inst2|dout[15]~1500 L15 } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 09 14:51:53 2005 " "Info: Processing ended: Tue Aug 09 14:51:53 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}