📄 block1.tan.qmsg

📁 暑假时参加电子设计大赛曾经用EDA开发实现液晶显示TJUCI学校名的一个小程序
💻 QMSG
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{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[8\]~1507 " "Info: Node ROM:inst2\|dout\[8\]~1507" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[8\]~1529 " "Info: Node ROM:inst2\|dout\[8\]~1529" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[10\]~1505 " "Info: Node ROM:inst2\|dout\[10\]~1505" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[10\]~1525 " "Info: Node ROM:inst2\|dout\[10\]~1525" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[11\]~1504 " "Info: Node ROM:inst2\|dout\[11\]~1504" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[11\]~1522 " "Info: Node ROM:inst2\|dout\[11\]~1522" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[12\]~1503 " "Info: Node ROM:inst2\|dout\[12\]~1503" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "ROM:inst2\|dout\[12\]~1519 " "Info: Node ROM:inst2\|dout\[12\]~1519" {  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}  } { { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } } { "F:/ledTJUCI/ROM.VHD" "" "" { Text "F:/ledTJUCI/ROM.VHD" 13 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "hzsel " "Info: Assuming node hzsel is an undefined clock" {  } { { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 128 -144 24 144 "hzsel" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "hzsel" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node clkin is an undefined clock" {  } { { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 248 -240 -72 264 "clkin" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock800:inst4\|clkout5k " "Info: Detected ripple clock clock800:inst4\|clkout5k as buffer" {  } { { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 13 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clock800:inst4\|clkout5k" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "hzsel register register AND1:inst\|dou\[0\] AND1:inst\|dou\[1\] 125.0 MHz Internal " "Info: Clock hzsel Internal fmax is restricted to 125.0 MHz between source register AND1:inst\|dou\[0\] and destination register AND1:inst\|dou\[1\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.300 ns + Longest register register " "Info: + Longest register to register delay is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AND1:inst\|dou\[0\] 1 REG LC2_B11 83 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B11; Fanout = 83; REG Node = 'AND1:inst\|dou\[0\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { AND1:inst|dou[0] } "NODE_NAME" } } } { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 2.300 ns AND1:inst\|dou\[1\] 2 REG LC6_B11 68 " "Info: 2: + IC(0.600 ns) + CELL(1.700 ns) = 2.300 ns; Loc. = LC6_B11; Fanout = 68; REG Node = 'AND1:inst\|dou\[1\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.300 ns" { AND1:inst|dou[0] AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 73.91 % " "Info: Total cell delay = 1.700 ns ( 73.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 26.09 % " "Info: Total interconnect delay = 0.600 ns ( 26.09 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.300 ns" { AND1:inst|dou[0] AND1:inst|dou[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "hzsel destination 7.400 ns + Shortest register " "Info: + Shortest clock path from clock hzsel to destination register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns hzsel 1 CLK PIN_52 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_52; Fanout = 3; CLK Node = 'hzsel'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { hzsel } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 128 -144 24 144 "hzsel" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 7.400 ns AND1:inst\|dou\[1\] 2 REG LC6_B11 68 " "Info: 2: + IC(3.900 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC6_B11; Fanout = 68; REG Node = 'AND1:inst\|dou\[1\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "3.900 ns" { hzsel AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 47.30 % " "Info: Total cell delay = 3.500 ns ( 47.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 52.70 % " "Info: Total interconnect delay = 3.900 ns ( 52.70 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "hzsel source 7.400 ns - Longest register " "Info: - Longest clock path from clock hzsel to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns hzsel 1 CLK PIN_52 3 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_52; Fanout = 3; CLK Node = 'hzsel'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { hzsel } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 128 -144 24 144 "hzsel" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.000 ns) 7.400 ns AND1:inst\|dou\[0\] 2 REG LC2_B11 83 " "Info: 2: + IC(3.900 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC2_B11; Fanout = 83; REG Node = 'AND1:inst\|dou\[0\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "3.900 ns" { hzsel AND1:inst|dou[0] } "NODE_NAME" } } } { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 47.30 % " "Info: Total cell delay = 3.500 ns ( 47.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 52.70 % " "Info: Total interconnect delay = 3.900 ns ( 52.70 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[0] } "NODE_NAME" } } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.300 ns" { AND1:inst|dou[0] AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "7.400 ns" { hzsel AND1:inst|dou[0] } "NODE_NAME" } } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { AND1:inst|dou[1] } "NODE_NAME" } } } { "F:/ledTJUCI/AND1.VHD" "" "" { Text "F:/ledTJUCI/AND1.VHD" 16 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register clock800:inst4\|count1\[1\] register clock800:inst4\|clkout5k 45.25 MHz 22.1 ns Internal " "Info: Clock clkin has Internal fmax of 45.25 MHz between source register clock800:inst4\|count1\[1\] and destination register clock800:inst4\|clkout5k (period= 22.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.500 ns + Longest register register " "Info: + Longest register to register delay is 18.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock800:inst4\|count1\[1\] 1 REG LC2_B16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B16; Fanout = 3; REG Node = 'clock800:inst4\|count1\[1\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { clock800:inst4|count1[1] } "NODE_NAME" } } } { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns clock800:inst4\|LessThan~185 2 COMB LC1_B16 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_B16; Fanout = 1; COMB Node = 'clock800:inst4\|LessThan~185'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.900 ns" { clock800:inst4|count1[1] clock800:inst4|LessThan~185 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 6.900 ns clock800:inst4\|LessThan~63 3 COMB LC1_B13 1 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 6.900 ns; Loc. = LC1_B13; Fanout = 1; COMB Node = 'clock800:inst4\|LessThan~63'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "4.000 ns" { clock800:inst4|LessThan~185 clock800:inst4|LessThan~63 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 10.900 ns clock800:inst4\|LessThan~77 4 COMB LC2_B14 11 " "Info: 4: + IC(2.200 ns) + CELL(1.800 ns) = 10.900 ns; Loc. = LC2_B14; Fanout = 11; COMB Node = 'clock800:inst4\|LessThan~77'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "4.000 ns" { clock800:inst4|LessThan~63 clock800:inst4|LessThan~77 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 13.800 ns clock800:inst4\|count1~11 5 COMB LC6_B14 1 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 13.800 ns; Loc. = LC6_B14; Fanout = 1; COMB Node = 'clock800:inst4\|count1~11'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.900 ns" { clock800:inst4|LessThan~77 clock800:inst4|count1~11 } "NODE_NAME" } } } { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 16.200 ns clock800:inst4\|LessThan~186 6 COMB LC8_B14 1 " "Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 16.200 ns; Loc. = LC8_B14; Fanout = 1; COMB Node = 'clock800:inst4\|LessThan~186'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.400 ns" { clock800:inst4|count1~11 clock800:inst4|LessThan~186 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 18.500 ns clock800:inst4\|clkout5k 7 REG LC1_B14 5 " "Info: 7: + IC(0.600 ns) + CELL(1.700 ns) = 18.500 ns; Loc. = LC1_B14; Fanout = 5; REG Node = 'clock800:inst4\|clkout5k'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.300 ns" { clock800:inst4|LessThan~186 clock800:inst4|clkout5k } "NODE_NAME" } } } { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.700 ns 63.24 % " "Info: Total cell delay = 11.700 ns ( 63.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.800 ns 36.76 % " "Info: Total interconnect delay = 6.800 ns ( 36.76 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "18.500 ns" { clock800:inst4|count1[1] clock800:inst4|LessThan~185 clock800:inst4|LessThan~63 clock800:inst4|LessThan~77 clock800:inst4|count1~11 clock800:inst4|LessThan~186 clock800:inst4|clkout5k } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clkin to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_1 11 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 11; CLK Node = 'clkin'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { clkin } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 248 -240 -72 264 "clkin" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns clock800:inst4\|clkout5k 2 REG LC1_B14 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B14; Fanout = 5; REG Node = 'clock800:inst4\|clkout5k'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.500 ns" { clkin clock800:inst4|clkout5k } "NODE_NAME" } } } { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "5.300 ns" { clkin clock800:inst4|clkout5k } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 5.300 ns - Longest register " "Info: - Longest clock path from clock clkin to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_1 11 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 11; CLK Node = 'clkin'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "" { clkin } "NODE_NAME" } } } { "F:/ledTJUCI/Block1.bdf" "" "" { Schematic "F:/ledTJUCI/Block1.bdf" { { 248 -240 -72 264 "clkin" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns clock800:inst4\|count1\[1\] 2 REG LC2_B16 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B16; Fanout = 3; REG Node = 'clock800:inst4\|count1\[1\]'" {  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "2.500 ns" { clkin clock800:inst4|count1[1] } "NODE_NAME" } } } { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "5.300 ns" { clkin clock800:inst4|count1[1] } "NODE_NAME" } } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "5.300 ns" { clkin clock800:inst4|clkout5k } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "5.300 ns" { clkin clock800:inst4|count1[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "F:/led2/clock800.vhd" "" "" { Text "F:/led2/clock800.vhd" 13 -1 0 } }  } 0}  } { { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "18.500 ns" { clock800:inst4|count1[1] clock800:inst4|LessThan~185 clock800:inst4|LessThan~63 clock800:inst4|LessThan~77 clock800:inst4|count1~11 clock800:inst4|LessThan~186 clock800:inst4|clkout5k } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "5.300 ns" { clkin clock800:inst4|clkout5k } "NODE_NAME" } } } { "F:/ledTJUCI/db/Block1_cmp.qrpt" "" "" { Report "F:/ledTJUCI/db/Block1_cmp.qrpt" Compiler "Block1" "UNKNOWN" "V1" "F:/ledTJUCI/db/Block1.quartus_db" { Floorplan "" "" "5.300 ns" { clkin clock800:inst4|count1[1] } "NODE_NAME" } } }  } 0}
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