block1.fit.eqn

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--D1L331 is ROM:inst2|Mux~403 at LC4_C3
--operation mode is normal

D1L331 = !J1_q[0] & (J1_q[3] & !J1_q[2] & !J1_q[1] # !J1_q[3] & (J1_q[2] $ J1_q[1]));


--D1L231 is ROM:inst2|Mux~401 at LC7_C6
--operation mode is normal

D1L231 = J1_q[2] & (J1_q[3] $ !J1_q[0] # !J1_q[1]) # !J1_q[2] & (J1_q[3] # J1_q[1] # J1_q[0]);


--D1L131 is ROM:inst2|Mux~399 at LC8_C6
--operation mode is normal

D1L131 = J1_q[3] & (!J1_q[0] # !J1_q[1] # !J1_q[2]) # !J1_q[3] & (J1_q[2] # J1_q[1] # J1_q[0]);


--D1L681 is ROM:inst2|Mux~603 at LC1_C6
--operation mode is normal

D1L681 = B1_dou[0] & (B1_dou[2] # !D1L231) # !B1_dou[0] & D1L131 & !B1_dou[2];


--D1L431 is ROM:inst2|Mux~405 at LC5_C3
--operation mode is normal

D1L431 = J1_q[3] & !J1_q[2] & !J1_q[1] & J1_q[0] # !J1_q[3] & J1_q[1] & !J1_q[0];


--D1L781 is ROM:inst2|Mux~604 at LC6_C3
--operation mode is normal

D1L781 = D1L681 & (D1L431 # !B1_dou[2]) # !D1L681 & B1_dou[2] & D1L331;


--D1L4 is ROM:inst2|dout[1]~1542 at LC7_C3
--operation mode is normal

D1L4 = D1L3 & (B1_dou[1] & D1L981 # !B1_dou[1] & D1L781);


--D1L5 is ROM:inst2|dout[1]~1543 at LC8_C3
--operation mode is normal

D1L5 = !CR & (B1_dou[1] & D1L981 # !B1_dou[1] & D1L781);


--D1L3 is ROM:inst2|dout[1]~1514 at LC3_C3
--operation mode is normal

D1L3 = D1L5 # D1L4 # CR & D1L3;


--D1L931 is ROM:inst2|Mux~418 at LC1_C1
--operation mode is normal

D1L931 = !J1_q[0] & (J1_q[3] & B1_dou[0] & !J1_q[1] # !J1_q[3] & !B1_dou[0] & J1_q[1]);


--D1L441 is ROM:inst2|Mux~531 at LC8_C8
--operation mode is normal

D1L441 = !J1_q[3] & B1_dou[0] & J1_q[1];


--D1L831 is ROM:inst2|Mux~415 at LC3_C5
--operation mode is normal

D1L831 = B1_dou[0] & !J1_q[1] & (J1_q[3] # J1_q[0]) # !B1_dou[0] & !J1_q[0] & (J1_q[3] $ J1_q[1]);


--D1L091 is ROM:inst2|Mux~607 at LC1_C8
--operation mode is normal

D1L091 = J1_q[2] & (D1L441 # B1_dou[1]) # !J1_q[2] & D1L831 & !B1_dou[1];


--D1L041 is ROM:inst2|Mux~420 at LC2_C1
--operation mode is normal

D1L041 = !B1_dou[0] & !J1_q[1] & (J1_q[3] $ J1_q[0]);


--D1L191 is ROM:inst2|Mux~608 at LC3_C1
--operation mode is normal

D1L191 = D1L091 & (D1L041 # !B1_dou[1]) # !D1L091 & B1_dou[1] & D1L931;


--D1L741 is ROM:inst2|Mux~557 at LC4_C1
--operation mode is normal

D1L741 = J1_q[2] & J1_q[1] & (B1_dou[1] $ J1_q[0]);


--D1L912 is ROM:inst2|Mux~2053 at LC6_C1
--operation mode is normal

D1L912 = !J1_q[0] & !J1_q[1] & !J1_q[2];


--D1L022 is ROM:inst2|Mux~2054 at LC7_C1
--operation mode is normal

D1L022 = B1_dou[0] & D1L741 # !B1_dou[0] & !B1_dou[1] & D1L912;


--D1L122 is ROM:inst2|Mux~2055 at LC8_C1
--operation mode is normal

D1L122 = B1_dou[2] & D1L191 # !B1_dou[2] & !J1_q[3] & D1L022;


--D1L1 is ROM:inst2|dout[0]~1515 at LC5_C1
--operation mode is normal

D1L1 = CR & D1L1 # !CR & D1L122;


--F1_clkout5k is clock800:inst4|clkout5k at LC1_B14
--operation mode is normal

F1_clkout5k_lut_out = F1L61 & (L1_unreg_res_node[9] # F1L81 & N3_cs_buffer[7]);
F1_clkout5k = DFFEA(F1_clkout5k_lut_out, GLOBAL(clkin), , , , , );


--F1_count1[2] is clock800:inst4|count1[2] at LC3_B16
--operation mode is normal

F1_count1[2]_lut_out = N3_cs_buffer[2] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[2] = DFFEA(F1_count1[2]_lut_out, GLOBAL(clkin), , , , , );


--F1_count1[1] is clock800:inst4|count1[1] at LC2_B16
--operation mode is normal

F1_count1[1]_lut_out = N3_cs_buffer[1] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[1] = DFFEA(F1_count1[1]_lut_out, GLOBAL(clkin), , , , , );


--F1L71 is clock800:inst4|LessThan~185 at LC1_B16
--operation mode is normal

F1L71 = !F1_count1[2] # !F1_count1[1];


--F1_count1[0] is clock800:inst4|count1[0] at LC4_B13
--operation mode is arithmetic

F1_count1[0]_lut_out = F1L61 & !F1_count1[0];
F1_count1[0] = DFFEA(F1_count1[0]_lut_out, GLOBAL(clkin), , , , , );

--N3_cout[0] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] at LC4_B13
--operation mode is arithmetic

N3_cout[0] = CARRY(F1_count1[0]);


--F1_count1[4] is clock800:inst4|count1[4] at LC2_B13
--operation mode is normal

F1_count1[4]_lut_out = N3_cs_buffer[4] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[4] = DFFEA(F1_count1[4]_lut_out, GLOBAL(clkin), , , , , );


--F1_count1[3] is clock800:inst4|count1[3] at LC3_B13
--operation mode is normal

F1_count1[3]_lut_out = N3_cs_buffer[3] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[3] = DFFEA(F1_count1[3]_lut_out, GLOBAL(clkin), , , , , );


--F1L41 is clock800:inst4|LessThan~63 at LC1_B13
--operation mode is normal

F1L41 = F1L71 # !F1_count1[0] # !F1_count1[4] # !F1_count1[3];


--F1_count1[7] is clock800:inst4|count1[7] at LC6_B15
--operation mode is normal

F1_count1[7]_lut_out = N3_cs_buffer[7] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[7] = DFFEA(F1_count1[7]_lut_out, GLOBAL(clkin), , , , , );


--F1_count1[6] is clock800:inst4|count1[6] at LC3_B14
--operation mode is normal

F1_count1[6]_lut_out = N3_cs_buffer[6] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[6] = DFFEA(F1_count1[6]_lut_out, GLOBAL(clkin), , , , , );


--F1_count1[5] is clock800:inst4|count1[5] at LC7_B15
--operation mode is normal

F1_count1[5]_lut_out = N3_cs_buffer[5] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[5] = DFFEA(F1_count1[5]_lut_out, GLOBAL(clkin), , , , , );


--F1L51 is clock800:inst4|LessThan~77 at LC2_B14
--operation mode is normal

F1L51 = !F1_count1[5] & !F1_count1[6] & !F1_count1[7] & F1L41;


--F1_count1[9] is clock800:inst4|count1[9] at LC5_B14
--operation mode is normal

F1_count1[9]_lut_out = L1_unreg_res_node[9] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[9] = DFFEA(F1_count1[9]_lut_out, GLOBAL(clkin), , , , , );


--F1_count1[8] is clock800:inst4|count1[8] at LC4_B14
--operation mode is normal

F1_count1[8]_lut_out = N3_cs_buffer[8] & (F1L51 # !F1_count1[9] # !F1_count1[8]);
F1_count1[8] = DFFEA(F1_count1[8]_lut_out, GLOBAL(clkin), , , , , );


--F1L61 is clock800:inst4|LessThan~83 at LC7_B14
--operation mode is normal

F1L61 = F1L51 # !F1_count1[9] # !F1_count1[8];


--N3_cs_buffer[7] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC3_B15
--operation mode is arithmetic

N3_cs_buffer[7] = F1_count1[7] $ N3_cout[6];

--N3_cout[7] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[7] at LC3_B15
--operation mode is arithmetic

N3_cout[7] = CARRY(F1_count1[7] & N3_cout[6]);


--N3_cs_buffer[8] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC4_B15
--operation mode is arithmetic

N3_cs_buffer[8] = F1_count1[8] $ N3_cout[7];

--N3_cout[8] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[8] at LC4_B15
--operation mode is arithmetic

N3_cout[8] = CARRY(F1_count1[8] & N3_cout[7]);


--F1L31 is clock800:inst4|count1~11 at LC6_B14
--operation mode is normal

F1L31 = N3_cs_buffer[8] & (F1L51 # !F1_count1[9] # !F1_count1[8]);


--N3_cs_buffer[6] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC2_B15
--operation mode is arithmetic

N3_cs_buffer[6] = F1_count1[6] $ N3_cout[5];

--N3_cout[6] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] at LC2_B15
--operation mode is arithmetic

N3_cout[6] = CARRY(F1_count1[6] & N3_cout[5]);


--N3_cs_buffer[5] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC1_B15
--operation mode is arithmetic

N3_cs_buffer[5] = F1_count1[5] $ N3_cout[4];

--N3_cout[5] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] at LC1_B15
--operation mode is arithmetic

N3_cout[5] = CARRY(F1_count1[5] & N3_cout[4]);


--N3_cs_buffer[4] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC8_B13
--operation mode is arithmetic

N3_cs_buffer[4] = F1_count1[4] $ N3_cout[3];

--N3_cout[4] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] at LC8_B13
--operation mode is arithmetic

N3_cout[4] = CARRY(F1_count1[4] & N3_cout[3]);


--F1L81 is clock800:inst4|LessThan~186 at LC8_B14
--operation mode is normal

F1L81 = F1L31 & (N3_cs_buffer[4] # N3_cs_buffer[5] # N3_cs_buffer[6]);


--D1L541 is ROM:inst2|Mux~547 at LC6_C15
--operation mode is normal

D1L541 = J1_q[2] & (!J1_q[0] # !J1_q[1]) # !J1_q[2] & (B1_dou[1] # J1_q[1] # J1_q[0]);


--D1L422 is ROM:inst2|Mux~2065 at LC4_C15
--operation mode is normal

D1L422 = (D1L541 # B1_dou[2] # J1_q[3] # !B1_dou[0]) & CASCADE(D1L522);


--N3_cs_buffer[2] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC6_B13
--operation mode is arithmetic

N3_cs_buffer[2] = F1_count1[2] $ N3_cout[1];

--N3_cout[2] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] at LC6_B13
--operation mode is arithmetic

N3_cout[2] = CARRY(F1_count1[2] & N3_cout[1]);


--N3_cs_buffer[1] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC5_B13
--operation mode is arithmetic

N3_cs_buffer[1] = F1_count1[1] $ N3_cout[0];

--N3_cout[1] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] at LC5_B13
--operation mode is arithmetic

N3_cout[1] = CARRY(F1_count1[1] & N3_cout[0]);


--N3_cs_buffer[3] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC7_B13
--operation mode is arithmetic

N3_cs_buffer[3] = F1_count1[3] $ N3_cout[2];

--N3_cout[3] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] at LC7_B13
--operation mode is arithmetic

N3_cout[3] = CARRY(F1_count1[3] & N3_cout[2]);


--L1_unreg_res_node[9] is clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[9] at LC5_B15
--operation mode is normal

L1_unreg_res_node[9] = N3_cout[8] $ F1_count1[9];


--D1L222 is ROM:inst2|Mux~2062 at LC7_C15
--operation mode is normal

D1L222 = !J1_q[2] & !J1_q[1] & B1_dou[2] & B1_dou[1];


--D1L322 is ROM:inst2|Mux~2063 at LC2_C15
--operation mode is normal

D1L322 = J1_q[3] # !D1L222 # !J1_q[0] # !B1_dou[0];


--D1L522 is ROM:inst2|Mux~2066 at LC3_C15
--operation mode is normal

D1L522 = (!D1L102 # !G1L5 # !J1_q[2] # !J1_q[1]) & CASCADE(D1L322);


--CR is CR at PIN_62
--operation mode is input

CR = INPUT();


--hzsel is hzsel at PIN_52
--operation mode is input

hzsel = INPUT();


--clkin is clkin at PIN_1
--operation mode is input

clkin = INPUT();


--L15 is L15 at PIN_49
--operation mode is output

L15 = OUTPUT(D1L54);


--L14 is L14 at PIN_48
--operation mode is output

L14 = OUTPUT(D1L34);


--L13 is L13 at PIN_47
--operation mode is output

L13 = OUTPUT(D1L14);


--L12 is L12 at PIN_16
--operation mode is output

L12 = OUTPUT(D1L73);


--L11 is L11 at PIN_17
--operation mode is output

L11 = OUTPUT(D1L33);


--L10 is L10 at PIN_18
--operation mode is output

L10 = OUTPUT(D1L92);


--L9 is L9 at PIN_19
--operation mode is output

L9 = OUTPUT(D1L72);


--L8 is L8 at PIN_72
--operation mode is output

L8 = OUTPUT(D1L32);


--L7 is L7 at PIN_21
--operation mode is output

L7 = OUTPUT(D1L12);


--L6 is L6 at PIN_22
--operation mode is output

L6 = OUTPUT(D1L91);


--L5 is L5 at PIN_23
--operation mode is output

L5 = OUTPUT(D1L71);


--L4 is L4 at PIN_24
--operation mode is output

L4 = OUTPUT(D1L31);


--L3 is L3 at PIN_25
--operation mode is output

L3 = OUTPUT(D1L11);


--L2 is L2 at PIN_27
--operation mode is output

L2 = OUTPUT(D1L7);


--L1 is L1 at PIN_28
--operation mode is output

L1 = OUTPUT(D1L3);


--L0 is L0 at PIN_29
--operation mode is output

L0 = OUTPUT(D1L1);


--G is G at PIN_58
--operation mode is output

G = OUTPUT(G1L6);


--F is F at PIN_59
--operation mode is output

F = OUTPUT(!G1L5);


--E is E at PIN_60
--operation mode is output

E = OUTPUT(!D1L291);


--D is D at PIN_61
--operation mode is output

D = OUTPUT(G1L4);


--C is C at PIN_65
--operation mode is output

C = OUTPUT(!G1L3);


--B is B at PIN_66
--operation mode is output

B = OUTPUT(G1L2);


--A is A at PIN_67
--operation mode is output

A = OUTPUT(G1L1);


--SEL3 is SEL3 at PIN_54
--operation mode is output

SEL3 = OUTPUT(A1L34);


--SEL2 is SEL2 at PIN_53
--operation mode is output

SEL2 = OUTPUT(A1L14);


--SEL1 is SEL1 at PIN_51
--operation mode is output

SEL1 = OUTPUT(A1L93);


--SEL0 is SEL0 at PIN_50
--operation mode is output

SEL0 = OUTPUT(A1L73);


--LED[7] is LED[7] at PIN_71
--operation mode is output

LED[7] = OUTPUT(E1L1);


--LED[6] is LED[6] at PIN_64
--operation mode is output

LED[6] = OUTPUT(E1L2);


--LED[5] is LED[5] at PIN_39
--operation mode is output

LED[5] = OUTPUT(E1L3);


--LED[4] is LED[4] at PIN_38
--operation mode is output

LED[4] = OUTPUT(E1L4);


--LED[3] is LED[3] at PIN_37
--operation mode is output

LED[3] = OUTPUT(E1L5);


--LED[2] is LED[2] at PIN_36
--operation mode is output

LED[2] = OUTPUT(!E1L7);


--LED[1] is LED[1] at PIN_35
--operation mode is output

LED[1] = OUTPUT(!D1L622);


--LED[0] is LED[0] at PIN_30
--operation mode is output

LED[0] = OUTPUT(E1L6);


--D1L622 is ROM:inst2|Mux~2069 at LC2_B6
--operation mode is normal

D1L622 = !B1_dou[1] & !B1_dou[2] & B1_dou[0];


--A1L34 is SEL3~0 at LC1_A21
--operation mode is normal

A1L34 = J1_q[3];


--A1L14 is SEL2~0 at LC1_C19
--operation mode is normal

A1L14 = J1_q[2];


--A1L93 is SEL1~0 at LC1_A18
--operation mode is normal

A1L93 = J1_q[1];


--A1L73 is SEL0~0 at LC4_A18
--operation mode is normal

A1L73 = J1_q[0];