deled.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DELED is port   
(CKDSP,A6,A5,A4:  in std_logic;   
T6,T5,T4,T3,T2,T1,T0: out std_logic);
end;
architecture arc_DELED of DELED is
signal d1in:  std_logic_vector(2 downto 0);
signal d1out:  std_logic_vector(6 downto 0);
begin
   d1in<=A6&A5&A4;
process(A4)     
begin          
--if(CKDSP='0')then 
case d1in is
   when"000"=>d1out<="0110000"; --1    
   when"001"=>d1out<="1101101"; --2    
   when"010"=>d1out<="1111001"; --3    
   when"011"=>d1out<="0110011"; --4
   when"100"=>d1out<="1011011"; --5    
   when"101"=>d1out<="1011111"; --6    
   when"110"=>d1out<="1110000"; --7    
   when"111"=>d1out<="1111111"; --8
   when others=>d1out<="0000000";
   end case;          
 --end if;
end process;
T6<=d1out(6);
T5<=d1out(5);
T4<=d1out(4);
T3<=d1out(3);
T2<=d1out(2);
T1<=d1out(1);
T0<=d1out(0); 
END arc_DELED;