block1.tan.rpt

来自「暑假时参加电子设计大赛曾经用EDA开发实现液晶显示TJUCI学校名的一个小程序」· RPT 代码 · 共 358 行 · 第 1/5 页

; Timing Analyzer Summary                                                                                                                                                                                                                       ;
+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------+-------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                 ; To                      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------+-------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 42.500 ns                                      ; ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; L11                     ; clkin      ;          ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 25.300 ns                                      ; CR                                                                   ; L4                      ;            ;          ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 17.000 ns                                      ; AND1:inst|dou[1]                                                     ; LED[5]                  ; hzsel      ;          ; 0            ;
; Worst-case Minimum tpd       ; N/A   ; None          ; 15.600 ns                                      ; CR                                                                   ; L15                     ;            ;          ; 0            ;
; Clock Setup: 'clkin'         ; N/A   ; None          ; 45.25 MHz ( period = 22.100 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|clkout5k ; clkin      ; clkin    ; 0            ;
; Clock Setup: 'hzsel'         ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; AND1:inst|dou[0]                                                     ; AND1:inst|dou[2]        ; hzsel      ; hzsel    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                      ;                         ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------+-------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; hzsel           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; clkin           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'hzsel'                                                                                                                                                                                     ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From             ; To               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; AND1:inst|dou[0] ; AND1:inst|dou[1] ; hzsel      ; hzsel    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; AND1:inst|dou[1] ; AND1:inst|dou[2] ; hzsel      ; hzsel    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; AND1:inst|dou[0] ; AND1:inst|dou[2] ; hzsel      ; hzsel    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; AND1:inst|dou[0] ; AND1:inst|dou[0] ; hzsel      ; hzsel    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; AND1:inst|dou[1] ; AND1:inst|dou[1] ; hzsel      ; hzsel    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; AND1:inst|dou[2] ; AND1:inst|dou[2] ; hzsel      ; hzsel    ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkin'                                                                                                                                                                                                                                                                                             ;
+-------+------------------------------------------------+----------------------------------------------------------------------+----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                 ; To                                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------------------------------------------------------+----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 45.25 MHz ( period = 22.100 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|clkout5k                                              ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 46.30 MHz ( period = 21.600 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|clkout5k                                              ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 48.08 MHz ( period = 20.800 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[0]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 49.26 MHz ( period = 20.300 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[0]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 53.48 MHz ( period = 18.700 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[1]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 53.48 MHz ( period = 18.700 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[2]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 53.76 MHz ( period = 18.600 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[3]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 53.76 MHz ( period = 18.600 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[4]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 53.76 MHz ( period = 18.600 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[7]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 53.76 MHz ( period = 18.600 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[5]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 54.64 MHz ( period = 18.300 ns )               ; clock800:inst4|count1[0]                                             ; clock800:inst4|clkout5k                                              ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 54.95 MHz ( period = 18.200 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[1]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 54.95 MHz ( period = 18.200 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[2]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 55.25 MHz ( period = 18.100 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[3]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 55.25 MHz ( period = 18.100 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[4]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 55.25 MHz ( period = 18.100 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[7]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 55.25 MHz ( period = 18.100 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[5]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 55.25 MHz ( period = 18.100 ns )               ; clock800:inst4|count1[4]                                             ; clock800:inst4|clkout5k                                              ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 55.25 MHz ( period = 18.100 ns )               ; clock800:inst4|count1[3]                                             ; clock800:inst4|clkout5k                                              ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 57.80 MHz ( period = 17.300 ns )               ; clock800:inst4|count1[6]                                             ; clock800:inst4|clkout5k                                              ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 58.82 MHz ( period = 17.000 ns )               ; clock800:inst4|count1[8]                                             ; clock800:inst4|clkout5k                                              ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 59.52 MHz ( period = 16.800 ns )               ; clock800:inst4|count1[0]                                             ; clock800:inst4|count1[0]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 59.52 MHz ( period = 16.800 ns )               ; clock800:inst4|count1[4]                                             ; clock800:inst4|count1[0]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 59.52 MHz ( period = 16.800 ns )               ; clock800:inst4|count1[3]                                             ; clock800:inst4|count1[0]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 59.52 MHz ( period = 16.800 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[6]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 59.52 MHz ( period = 16.800 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[8]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 59.52 MHz ( period = 16.800 ns )               ; clock800:inst4|count1[1]                                             ; clock800:inst4|count1[9]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 61.35 MHz ( period = 16.300 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[6]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; 61.35 MHz ( period = 16.300 ns )               ; clock800:inst4|count1[2]                                             ; clock800:inst4|count1[8]                                             ; clkin      ; clkin    ; None                        ; None                      ; None                    ;