block1.map.rpt

暑假时参加电子设计大赛曾经用EDA开发实现液晶显示TJUCI学校名的一个小程序

+--------------------------------+
The equations can be found in F:/ledTJUCI/Block1.map.eqn.


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                              ;
+-------------------------------------------------------------------+-----------------+
; File Name                                                         ; Used in Netlist ;
+-------------------------------------------------------------------+-----------------+
; YIMAQI.vhd                                                        ; yes             ;
; AND1.VHD                                                          ; yes             ;
; ANDL.VHD                                                          ; yes             ;
; ROM.VHD                                                           ; yes             ;
; Block1.bdf                                                        ; yes             ;
; DELED.vhd                                                         ; yes             ;
; clock800.vhd                                                      ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc      ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/flex10ke_lcell.inc    ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/addcore.inc           ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/addcore.tdf           ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/altshift.tdf          ; yes             ;
+-------------------------------------------------------------------+-----------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                              ;
+-----------------------------------+----------------------------------------------------------------------+
; Resource                          ; Usage                                                                ;
+-----------------------------------+----------------------------------------------------------------------+
; Logic cells                       ; 255                                                                  ;
; Total combinational functions     ; 254                                                                  ;
; Total 4-input functions           ; 200                                                                  ;
; Total 3-input functions           ; 36                                                                   ;
; Total 2-input functions           ; 5                                                                    ;
; Total 1-input functions           ; 9                                                                    ;
; Total 0-input functions           ; 4                                                                    ;
; Combinational cells for routing   ; 0                                                                    ;
; Total registers                   ; 18                                                                   ;
; Total logic cells in carry chains ; 14                                                                   ;
; I/O pins                          ; 38                                                                   ;
; Maximum fan-out node              ; ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ;
; Maximum fan-out                   ; 101                                                                  ;
; Total fan-out                     ; 1002                                                                 ;
; Average fan-out                   ; 3.42                                                                 ;
+-----------------------------------+----------------------------------------------------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 20    ;
; Number of synthesis-generated cells                    ; 235   ;
; Number of WYSIWYG LUTs                                 ; 20    ;
; Number of synthesis-generated LUTs                     ; 234   ;
; Number of WYSIWYG registers                            ; 4     ;
; Number of synthesis-generated registers                ; 14    ;
; Number of cells with combinational logic only          ; 237   ;
; Number of cells with registers only                    ; 1     ;
; Number of cells with combinational logic and registers ; 17    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 7     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Aug 09 14:51:36 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Block1 -c Block1
Info: Found 2 design units, including 1 entities, in source file clock2500.vhd
    Info: Found design unit 1: clock2500-arc
    Info: Found entity 1: clock2500
Info: Found 2 design units, including 1 entities, in source file YIMAQI.vhd
    Info: Found design unit 1: YIMAQI-arc_YIMAQI
    Info: Found entity 1: YIMAQI
Info: Found 2 design units, including 1 entities, in source file AND1.VHD
    Info: Found design unit 1: AND1-ARC_AND1
    Info: Found entity 1: AND1
Info: Found 2 design units, including 1 entities, in source file ANDL.VHD
    Info: Found design unit 1: ANDL-ARC_ANDL
    Info: Found entity 1: ANDL
Info: Found 2 design units, including 1 entities, in source file ROM.VHD
    Info: Found design unit 1: ROM-arc_ROM
    Info: Found entity 1: ROM
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Found 2 design units, including 1 entities, in source file DELED.vhd
    Info: Found design unit 1: DELED-arc_DELED
    Info: Found entity 1: DELED
Info: Found 2 design units, including 1 entities, in source file clock800.vhd
    Info: Found design unit 1: clock800-arc
    Info: Found entity 1: clock800
Warning: VHDL Process Statement warning at ROM.VHD(15): signal cr is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at ROM.VHD(154): OTHERS choice is never selected
Warning: VHDL Process Statement warning at ROM.VHD(13): signal or variable dout may not be assigned a new value in every possible path through the Process Statement. Signal or variable dout holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at DELED.vhd(16): signal d1in is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at DELED.vhd(25): OTHERS choice is never selected
Warning: VHDL Process Statement warning at YIMAQI.vhd(14): signal d2in is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at YIMAQI.vhd(23): OTHERS choice is never selected
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: ANDL:inst1|dou[0]~4
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 16 buffer(s)
    Info: Ignored 16 SOFT buffer(s)
Info: Implemented 293 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 35 output pins
    Info: Implemented 255 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue Aug 09 14:51:41 2005
    Info: Elapsed time: 00:00:05