📄 yimaqi.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity YIMAQI is port
(CKDSP,A2,A1,A0: in std_logic;
LED: out std_logic_vector(7 downto 0));
end;
architecture arc_YIMAQI of YIMAQI is
signal d2in: std_logic_vector(2 downto 0);
begin
d2in<=A2&A1&A0;
process(CKDSP)
begin
case d2in is
when"000"=>LED<="11111110"; --1
when"001"=>LED<="11111101"; --2
when"010"=>LED<="11111011"; --3
when"011"=>LED<="11110111"; --4
when"100"=>LED<="11101111"; --5
when"101"=>LED<="11011111"; --6
when"110"=>LED<="10111111"; --7
when"111"=>LED<="01111111"; --8
when others=>LED<="00000000";
end case;
end process;
END arc_YIMAQI;
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