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📄 inter_mux_rfec.rpt

📁 在Maxplus软件平台开发的
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D16      8/ 8(100%)   2/ 8( 25%)   0/ 8(  0%)    2/2    1/2      11/22( 50%)   
D17      8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    2/2    1/2       4/22( 18%)   
D18      8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    2/2    1/2       8/22( 36%)   
D19      8/ 8(100%)   1/ 8( 12%)   4/ 8( 50%)    2/2    1/2       4/22( 18%)   
D20      8/ 8(100%)   2/ 8( 25%)   0/ 8(  0%)    2/2    1/2       9/22( 40%)   
D21      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       1/22(  4%)   
D22      7/ 8( 87%)   0/ 8(  0%)   4/ 8( 50%)    2/2    1/2       1/22(  4%)   
D23      4/ 8( 50%)   1/ 8( 12%)   0/ 8(  0%)    1/2    0/2       7/22( 31%)   
D24      8/ 8(100%)   2/ 8( 25%)   1/ 8( 12%)    2/2    1/2       9/22( 40%)   
E13      8/ 8(100%)   1/ 8( 12%)   2/ 8( 25%)    2/2    1/2       4/22( 18%)   
E17      8/ 8(100%)   2/ 8( 25%)   0/ 8(  0%)    2/2    1/2       9/22( 40%)   
E18      8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    2/2    1/2       4/22( 18%)   
F1       7/ 8( 87%)   1/ 8( 12%)   4/ 8( 50%)    2/2    1/2       1/22(  4%)   
F2       8/ 8(100%)   1/ 8( 12%)   1/ 8( 12%)    2/2    1/2      11/22( 50%)   
F3       8/ 8(100%)   2/ 8( 25%)   0/ 8(  0%)    2/2    1/2      11/22( 50%)   
F4       8/ 8(100%)   2/ 8( 25%)   1/ 8( 12%)    2/2    1/2      10/22( 45%)   
F6       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    2/2    1/2       8/22( 36%)   
F7       8/ 8(100%)   2/ 8( 25%)   3/ 8( 37%)    2/2    1/2       1/22(  4%)   
F8       3/ 8( 37%)   0/ 8(  0%)   2/ 8( 25%)    2/2    1/2       1/22(  4%)   
F9       7/ 8( 87%)   0/ 8(  0%)   3/ 8( 37%)    2/2    1/2       4/22( 18%)   
F10      8/ 8(100%)   1/ 8( 12%)   2/ 8( 25%)    2/2    1/2       8/22( 36%)   
F11      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    2/2    1/2       5/22( 22%)   
F12      7/ 8( 87%)   1/ 8( 12%)   2/ 8( 25%)    2/2    1/2       4/22( 18%)   
F13      8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    2/2    1/2       1/22(  4%)   
F14      3/ 8( 37%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       4/22( 18%)   
F16      8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    2/2    1/2       1/22(  4%)   
F19      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    1/2    0/2       1/22(  4%)   
F20      8/ 8(100%)   1/ 8( 12%)   1/ 8( 12%)    2/2    1/2       8/22( 36%)   
F23      8/ 8(100%)   1/ 8( 12%)   1/ 8( 12%)    2/2    1/2      11/22( 50%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 6/6      (100%)
Total I/O pins used:                            17/96     ( 17%)
Total logic cells used:                        558/1152   ( 48%)
Total embedded cells used:                       0/48     (  0%)
Total EABs used:                                 0/6      (  0%)
Average fan-in:                                 1.91/4    ( 47%)
Total fan-in:                                1069/4608    ( 23%)

Total input pins required:                      15
Total input I/O cell registers required:         0
Total output pins required:                      8
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                    558
Total flipflops required:                      384
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                        43/1152   (  3%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 B:      7   0   0   8   0   8   8   8   0   8   8   8   0   8   3   8   8   5   8   7   8   8   0   8   0    134/0  
 C:      5   8   1   8   8   7   3   8   8   8   8   8   0   0   8   8   8   8   8   0   0   0   6   0   8    134/0  
 D:      0   7   7   0   6   8   8   4   8   7   8   7   0   7   5   8   8   8   8   8   8   1   7   4   8    150/0  
 E:      0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   0   8   8   0   0   0   0   0   0     24/0  
 F:      7   8   8   8   0   8   8   3   7   8   8   7   0   8   3   0   8   0   0   1   8   0   0   8   0    116/0  

Total:  19  23  16  24  14  31  27  23  23  31  32  30   0  31  19  24  32  29  32  16  24   9  13  20  16    558/0  



Device-Specific Information:           e:\work\maxplus\recv\inter_mux_rfec.rpt
inter_mux_rfec

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  56      -     -    -    --      INPUT                0    0    0   96  AD0
 124      -     -    -    --      INPUT                0    0    0   94  AD1
 126      -     -    -    --      INPUT                0    0    0   48  AD2
 117      -     -    -    05      INPUT                0    0    0   24  AD3
  54      -     -    -    --      INPUT  G             0    0    0    0  /CLR_L
  96      -     -    B    --      INPUT                0    0    0    1  D0
  97      -     -    B    --      INPUT                0    0    0    1  D1
  99      -     -    B    --      INPUT                0    0    0    1  D2
   9      -     -    B    --      INPUT                0    0    0    1  D3
  10      -     -    B    --      INPUT                0    0    0    1  D4
  98      -     -    B    --      INPUT                0    0    0    1  D5
  36      -     -    -    24      INPUT                0    0    0    1  D6
  95      -     -    B    --      INPUT                0    0    0    1  D7
 125      -     -    -    --      INPUT  G             0    0    0    0  LOCKCLK
  55      -     -    -    --      INPUT  G             0    0    0    0  OUTCLK


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:           e:\work\maxplus\recv\inter_mux_rfec.rpt
inter_mux_rfec

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  90      -     -    C    --     OUTPUT                0    1    0    0  RFEC0
  92      -     -    C    --     OUTPUT                0    1    0    0  RFEC1
  91      -     -    C    --     OUTPUT                0    1    0    0  RFEC2
  11      -     -    C    --     OUTPUT                0    1    0    0  RFEC3
  14      -     -    C    --     OUTPUT                0    1    0    0  RFEC4
  13      -     -    C    --     OUTPUT                0    1    0    0  RFEC5
  12      -     -    C    --     OUTPUT                0    1    0    0  RFEC6
  89      -     -    C    --     OUTPUT                0    1    0    0  RFEC7


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:           e:\work\maxplus\recv\inter_mux_rfec.rpt
inter_mux_rfec

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      4     -    C    15        OR2    s           1    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:54|~46~1
   -      8     -    C    18        OR2    s           1    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:54|~51~1
   -      6     -    C    11        OR2                2    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:73|:46
   -      8     -    C    11        OR2                2    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:73|:51
   -      5     -    C    10        OR2                2    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:92|:46
   -      6     -    C    10        OR2                2    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:92|:51
   -      7     -    C    10        OR2                2    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:111|:46
   -      2     -    C    07        OR2                2    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:111|:51
   -      8     -    C    10        OR2    s           2    2    0    1  |LPM_MUX:35|muxlut:281|muxlut:130|~46~1
   -      1     -    C    10        OR2                1    3    0    3  |LPM_MUX:35|muxlut:281|muxlut:130|:46
   -      3     -    C    18        OR2                2    2    0    3  |LPM_MUX:35|muxlut:281|muxlut:130|:50
   -      1     -    C    11        OR2    s           2    2    0    3  |LPM_MUX:35|muxlut:281|muxlut:130|~51~1

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