📄 inter_mux_rfec.rpt
字号:
|rfec:39|rfecpre:68|12and:31|
|rfec:39|rfecpre:68|12and:30|
Device-Specific Information: e:\work\maxplus\recv\inter_mux_rfec.rpt
inter_mux_rfec
***** Logic for device 'inter_mux_rfec' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E L E E E E E E E E E E E E
S S S S S S S S S S S S S S G O V S S S S S S S S S S S S
E E E E E G E E E E V E E E E G E N C C E E E E E E V E E E E E E
R R R R R N R R R R C R R R R N R D K C R R R R R R C R R R R R R
V V V V V D V V V V C V V V V D V I A C A I V V V V V A V C V V V V V V
E E E E E I E E E E I E E E E I E N D L D N E E E E E D E I E E E E E E
D D D D D O D D D D O D D D D O D T 2 K 1 T D D D D D 3 D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
D3 | 9 100 | RESERVED
D4 | 10 99 | D2
RFEC3 | 11 98 | D5
RFEC6 | 12 97 | D1
RFEC5 | 13 96 | D0
RFEC4 | 14 95 | D7
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RFEC1
RESERVED | 18 91 | RFEC2
RESERVED | 19 EPF10K20TC144-3 90 | RFEC0
RESERVED | 20 89 | RFEC7
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
D6 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R G R V V / O A G G R R V R R R R G R R R R V R
E E E N E E E E C E E E E N E C C C U D N N E E C E E E E N E E E E C E
S S S D S S S S C S S S S D S C C L T 0 D D S S C S S S S D S S S S C S
E E E I E E E E I E E E E I E I I R C I I E E I E E E E I E E E E I E
R R R O R R R R O R R R R O R N N _ L N N R R O R R R R O R R R R O R
V V V V V V V V V V V V T T L K T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\work\maxplus\recv\inter_mux_rfec.rpt
inter_mux_rfec
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B1 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 4/22( 18%)
B4 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
B6 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
B7 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 8/22( 36%)
B8 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 11/22( 50%)
B10 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 2/2 1/2 11/22( 50%)
B11 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 8/22( 36%)
B12 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
B13 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
B14 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
B15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 8/22( 36%)
B16 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 8/22( 36%)
B17 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
B18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
B19 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
B20 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 8/22( 36%)
B21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 4/22( 18%)
B23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 8/22( 36%)
C1 5/ 8( 62%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
C2 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
C3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C4 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
C6 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
C7 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
C8 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
C9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
C10 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C11 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 8/22( 36%)
C12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
C14 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 14/22( 63%)
C15 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
C16 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 12/22( 54%)
C17 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 14/22( 63%)
C18 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 6/22( 27%)
C22 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
C24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 8/22( 36%)
D2 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D3 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 8/22( 36%)
D5 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
D6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 4/22( 18%)
D7 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 11/22( 50%)
D8 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D9 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 8/22( 36%)
D10 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
D11 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 11/22( 50%)
D12 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D13 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 5/22( 22%)
D14 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
D15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 4/22( 18%)
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