24bitshift.rpt

在Maxplus软件平台开发的

-- Node name is '|74595a:18|:22' = '|74595a:18|QF' 
-- Equation name is '_LC3_C7', type is buried 
_LC3_C7  = DFFE( _LC2_C7, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:18|:25' = '|74595a:18|QG' 
-- Equation name is '_LC5_C7', type is buried 
_LC5_C7  = DFFE( _LC4_C7, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:18|:28' = '|74595a:18|QH' 
-- Equation name is '_LC7_C7', type is buried 
_LC7_C7  = DFFE( _LC8_C7, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:18|:27' = '|74595a:18|QHN' 
-- Equation name is '_LC8_C7', type is buried 
_LC8_C7  = DFFE( _LC4_C7, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:18|:6' 
-- Equation name is '_LC2_A8', type is buried 
_LC2_A8  = DFFE( SER_DATA, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:18|:7' 
-- Equation name is '_LC4_A8', type is buried 
_LC4_A8  = DFFE( _LC2_A8, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:18|:14' 
-- Equation name is '_LC5_A8', type is buried 
_LC5_A8  = DFFE( _LC4_A8, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:18|:15' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = DFFE( _LC5_A8, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:18|:20' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = DFFE( _LC2_A1, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:18|:21' 
-- Equation name is '_LC2_C7', type is buried 
_LC2_C7  = DFFE( _LC1_A1, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:18|:26' 
-- Equation name is '_LC4_C7', type is buried 
_LC4_C7  = DFFE( _LC2_C7, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:8' = '|74595a:19|QA' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = DFFE( _LC5_C16, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:10' = '|74595a:19|QB' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = DFFE( _LC6_C16, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:13' = '|74595a:19|QC' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = DFFE( _LC7_C16, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:16' = '|74595a:19|QD' 
-- Equation name is '_LC4_A24', type is buried 
_LC4_A24 = DFFE( _LC4_C16, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:19' = '|74595a:19|QE' 
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = DFFE( _LC5_A24, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:22' = '|74595a:19|QF' 
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = DFFE( _LC6_A24, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:25' = '|74595a:19|QG' 
-- Equation name is '_LC3_A24', type is buried 
_LC3_A24 = DFFE( _LC8_A24, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:28' = '|74595a:19|QH' 
-- Equation name is '_LC7_C24', type is buried 
_LC7_C24 = DFFE( _LC2_A24, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:19|:27' = '|74595a:19|QHN' 
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = DFFE( _LC8_A24, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:6' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = DFFE( _LC8_C7, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:7' 
-- Equation name is '_LC6_C16', type is buried 
_LC6_C16 = DFFE( _LC5_C16, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:14' 
-- Equation name is '_LC7_C16', type is buried 
_LC7_C16 = DFFE( _LC6_C16, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:15' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = DFFE( _LC7_C16, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:20' 
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = DFFE( _LC4_C16, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:21' 
-- Equation name is '_LC6_A24', type is buried 
_LC6_A24 = DFFE( _LC5_A24, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:19|:26' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = DFFE( _LC6_A24, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:8' = '|74595a:20|QA' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = DFFE( _LC2_B13, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:10' = '|74595a:20|QB' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = DFFE( _LC4_B13, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:13' = '|74595a:20|QC' 
-- Equation name is '_LC5_B13', type is buried 
_LC5_B13 = DFFE( _LC8_B13, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:16' = '|74595a:20|QD' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = DFFE( _LC6_B13, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:19' = '|74595a:20|QE' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = DFFE( _LC2_B4, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:22' = '|74595a:20|QF' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = DFFE( _LC3_B4, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:25' = '|74595a:20|QG' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = DFFE( _LC5_B4, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:28' = '|74595a:20|QH' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = DFFE( _LC8_B4, GLOBAL( OUTCLK),  VCC,  VCC,  VCC);

-- Node name is '|74595a:20|:27' = '|74595a:20|QHN' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = DFFE( _LC5_B4, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:6' 
-- Equation name is '_LC2_B13', type is buried 
_LC2_B13 = DFFE( _LC2_A24, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:7' 
-- Equation name is '_LC4_B13', type is buried 
_LC4_B13 = DFFE( _LC2_B13, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:14' 
-- Equation name is '_LC8_B13', type is buried 
_LC8_B13 = DFFE( _LC4_B13, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:15' 
-- Equation name is '_LC6_B13', type is buried 
_LC6_B13 = DFFE( _LC8_B13, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:20' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = DFFE( _LC6_B13, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:21' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = DFFE( _LC2_B4, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);

-- Node name is '|74595a:20|:26' 
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = DFFE( _LC3_B4, GLOBAL( LOCKCLK), GLOBAL( /CLR_L),  VCC,  VCC);



Project Information                        e:\work\maxplus\recv\24bitshift.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,031K