📄 24bitshift.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 08 DFFE + 1 0 0 2 |74595a:18|:6
- 4 - A 08 DFFE + 0 1 0 2 |74595a:18|:7
- 1 - A 08 DFFE + 0 1 1 0 |74595a:18|QA (|74595a:18|:8)
- 7 - A 08 DFFE + 0 1 1 0 |74595a:18|QB (|74595a:18|:10)
- 3 - A 08 DFFE + 0 1 1 0 |74595a:18|QC (|74595a:18|:13)
- 5 - A 08 DFFE + 0 1 0 2 |74595a:18|:14
- 2 - A 01 DFFE + 0 1 0 2 |74595a:18|:15
- 5 - A 01 DFFE + 0 1 1 0 |74595a:18|QD (|74595a:18|:16)
- 1 - C 07 DFFE + 0 1 1 0 |74595a:18|QE (|74595a:18|:19)
- 1 - A 01 DFFE + 0 1 0 2 |74595a:18|:20
- 2 - C 07 DFFE + 0 1 0 2 |74595a:18|:21
- 3 - C 07 DFFE + 0 1 1 0 |74595a:18|QF (|74595a:18|:22)
- 5 - C 07 DFFE + 0 1 1 0 |74595a:18|QG (|74595a:18|:25)
- 4 - C 07 DFFE + 0 1 0 2 |74595a:18|:26
- 8 - C 07 DFFE + 0 1 0 2 |74595a:18|QHN (|74595a:18|:27)
- 7 - C 07 DFFE + 0 1 1 0 |74595a:18|QH (|74595a:18|:28)
- 5 - C 16 DFFE + 0 1 0 2 |74595a:19|:6
- 6 - C 16 DFFE + 0 1 0 2 |74595a:19|:7
- 3 - C 16 DFFE + 0 1 1 0 |74595a:19|QA (|74595a:19|:8)
- 1 - C 16 DFFE + 0 1 1 0 |74595a:19|QB (|74595a:19|:10)
- 2 - C 16 DFFE + 0 1 1 0 |74595a:19|QC (|74595a:19|:13)
- 7 - C 16 DFFE + 0 1 0 2 |74595a:19|:14
- 4 - C 16 DFFE + 0 1 0 2 |74595a:19|:15
- 4 - A 24 DFFE + 0 1 1 0 |74595a:19|QD (|74595a:19|:16)
- 1 - A 24 DFFE + 0 1 1 0 |74595a:19|QE (|74595a:19|:19)
- 5 - A 24 DFFE + 0 1 0 2 |74595a:19|:20
- 6 - A 24 DFFE + 0 1 0 2 |74595a:19|:21
- 7 - A 24 DFFE + 0 1 1 0 |74595a:19|QF (|74595a:19|:22)
- 3 - A 24 DFFE + 0 1 1 0 |74595a:19|QG (|74595a:19|:25)
- 8 - A 24 DFFE + 0 1 0 2 |74595a:19|:26
- 2 - A 24 DFFE + 0 1 0 2 |74595a:19|QHN (|74595a:19|:27)
- 7 - C 24 DFFE + 0 1 1 0 |74595a:19|QH (|74595a:19|:28)
- 2 - B 13 DFFE + 0 1 0 2 |74595a:20|:6
- 4 - B 13 DFFE + 0 1 0 2 |74595a:20|:7
- 3 - B 13 DFFE + 0 1 1 0 |74595a:20|QA (|74595a:20|:8)
- 7 - B 13 DFFE + 0 1 1 0 |74595a:20|QB (|74595a:20|:10)
- 5 - B 13 DFFE + 0 1 1 0 |74595a:20|QC (|74595a:20|:13)
- 8 - B 13 DFFE + 0 1 0 2 |74595a:20|:14
- 6 - B 13 DFFE + 0 1 0 2 |74595a:20|:15
- 1 - B 13 DFFE + 0 1 1 0 |74595a:20|QD (|74595a:20|:16)
- 7 - B 04 DFFE + 0 1 1 0 |74595a:20|QE (|74595a:20|:19)
- 2 - B 04 DFFE + 0 1 0 2 |74595a:20|:20
- 3 - B 04 DFFE + 0 1 0 2 |74595a:20|:21
- 4 - B 04 DFFE + 0 1 1 0 |74595a:20|QF (|74595a:20|:22)
- 6 - B 04 DFFE + 0 1 1 0 |74595a:20|QG (|74595a:20|:25)
- 5 - B 04 DFFE + 0 1 0 2 |74595a:20|:26
- 8 - B 04 DFFE + 0 1 0 1 |74595a:20|QHN (|74595a:20|:27)
- 1 - B 04 DFFE + 0 1 1 0 |74595a:20|QH (|74595a:20|:28)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 3/ 48( 6%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 4/ 96( 4%) 2/ 48( 4%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 3/ 96( 3%) 3/ 48( 6%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 LOCKCLK
INPUT 24 OUTCLK
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 /CLR_L
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** EQUATIONS **
LOCKCLK : INPUT;
OUTCLK : INPUT;
SER_DATA : INPUT;
/CLR_L : INPUT;
-- Node name is 'OUTD0_0'
-- Equation name is 'OUTD0_0', type is output
OUTD0_0 = _LC1_C16;
-- Node name is 'OUTD0_1'
-- Equation name is 'OUTD0_1', type is output
OUTD0_1 = _LC4_A24;
-- Node name is 'OUTD0_2'
-- Equation name is 'OUTD0_2', type is output
OUTD0_2 = _LC7_A24;
-- Node name is 'OUTD0_3'
-- Equation name is 'OUTD0_3', type is output
OUTD0_3 = _LC7_C24;
-- Node name is 'OUTD0_4'
-- Equation name is 'OUTD0_4', type is output
OUTD0_4 = _LC7_B13;
-- Node name is 'OUTD0_5'
-- Equation name is 'OUTD0_5', type is output
OUTD0_5 = _LC1_B13;
-- Node name is 'OUTD0_6'
-- Equation name is 'OUTD0_6', type is output
OUTD0_6 = _LC4_B4;
-- Node name is 'OUTD0_7'
-- Equation name is 'OUTD0_7', type is output
OUTD0_7 = _LC1_B4;
-- Node name is 'OUTD1_0'
-- Equation name is 'OUTD1_0', type is output
OUTD1_0 = _LC3_C16;
-- Node name is 'OUTD1_1'
-- Equation name is 'OUTD1_1', type is output
OUTD1_1 = _LC2_C16;
-- Node name is 'OUTD1_2'
-- Equation name is 'OUTD1_2', type is output
OUTD1_2 = _LC1_A24;
-- Node name is 'OUTD1_3'
-- Equation name is 'OUTD1_3', type is output
OUTD1_3 = _LC3_A24;
-- Node name is 'OUTD1_4'
-- Equation name is 'OUTD1_4', type is output
OUTD1_4 = _LC3_B13;
-- Node name is 'OUTD1_5'
-- Equation name is 'OUTD1_5', type is output
OUTD1_5 = _LC5_B13;
-- Node name is 'OUTD1_6'
-- Equation name is 'OUTD1_6', type is output
OUTD1_6 = _LC7_B4;
-- Node name is 'OUTD1_7'
-- Equation name is 'OUTD1_7', type is output
OUTD1_7 = _LC6_B4;
-- Node name is 'OUTFD0_0'
-- Equation name is 'OUTFD0_0', type is output
OUTFD0_0 = _LC7_A8;
-- Node name is 'OUTFD0_1'
-- Equation name is 'OUTFD0_1', type is output
OUTFD0_1 = _LC5_A1;
-- Node name is 'OUTFD0_2'
-- Equation name is 'OUTFD0_2', type is output
OUTFD0_2 = _LC3_C7;
-- Node name is 'OUTFD0_3'
-- Equation name is 'OUTFD0_3', type is output
OUTFD0_3 = _LC7_C7;
-- Node name is 'OUTFD1_0'
-- Equation name is 'OUTFD1_0', type is output
OUTFD1_0 = _LC1_A8;
-- Node name is 'OUTFD1_1'
-- Equation name is 'OUTFD1_1', type is output
OUTFD1_1 = _LC3_A8;
-- Node name is 'OUTFD1_2'
-- Equation name is 'OUTFD1_2', type is output
OUTFD1_2 = _LC1_C7;
-- Node name is 'OUTFD1_3'
-- Equation name is 'OUTFD1_3', type is output
OUTFD1_3 = _LC5_C7;
-- Node name is '|74595a:18|:8' = '|74595a:18|QA'
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = DFFE( _LC2_A8, GLOBAL( OUTCLK), VCC, VCC, VCC);
-- Node name is '|74595a:18|:10' = '|74595a:18|QB'
-- Equation name is '_LC7_A8', type is buried
_LC7_A8 = DFFE( _LC4_A8, GLOBAL( OUTCLK), VCC, VCC, VCC);
-- Node name is '|74595a:18|:13' = '|74595a:18|QC'
-- Equation name is '_LC3_A8', type is buried
_LC3_A8 = DFFE( _LC5_A8, GLOBAL( OUTCLK), VCC, VCC, VCC);
-- Node name is '|74595a:18|:16' = '|74595a:18|QD'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _LC2_A1, GLOBAL( OUTCLK), VCC, VCC, VCC);
-- Node name is '|74595a:18|:19' = '|74595a:18|QE'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = DFFE( _LC1_A1, GLOBAL( OUTCLK), VCC, VCC, VCC);
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