📄 24bitshift.rpt
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Project Information e:\work\maxplus\recv\24bitshift.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 02/19/2003 10:19:53
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
24bitshift
EPF10K10LC84-3 4 24 0 0 0 % 48 8 %
User Pins: 4 24 0
Project Information e:\work\maxplus\recv\24bitshift.rpt
** FILE HIERARCHY **
|74595a:18|
|74595a:19|
|74595a:20|
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
***** Logic for device '24bitshift' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R R R R R R R O
E E E E E E E E E E E E E N
S S S S S S S V S / O G S G S S S S F
E E E E E E E C E C U N E N E E E E _ ^
R R R R R R R C R L T D R D R R R R # D n
V V V V V V V I V R C I V I V V V V T O C
E E E E E E E N E _ L N E N E E E E C N E
D D D D D D D T D L K T D T D D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | OUTD1_2
^nCE | 14 72 | OUTD1_3
#TDI | 15 71 | OUTD0_1
OUTFD1_0 | 16 70 | RESERVED
OUTFD1_1 | 17 69 | OUTD0_2
OUTFD0_1 | 18 68 | GNDINT
OUTFD0_0 | 19 67 | OUTD0_5
VCCINT | 20 66 | OUTD1_4
OUTD0_7 | 21 65 | OUTD1_5
RESERVED | 22 EPF10K10LC84-3 64 | OUTD0_4
OUTD0_6 | 23 63 | VCCINT
OUTD1_7 | 24 62 | OUTD0_0
OUTD1_6 | 25 61 | OUTD1_1
GNDINT | 26 60 | OUTD1_0
OUTFD1_2 | 27 59 | RESERVED
OUTFD0_2 | 28 58 | OUTD0_3
OUTFD1_3 | 29 57 | #TMS
OUTFD0_3 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G S L G V G R R R R R R R
C n E E E E E C N E O N C N E E E E E E E
C C S S S S S C D R C D C D S S S S S S S
I O E E E E E I I _ K I I I E E E E E E E
N N R R R R R N N D C N N N R R R R R R R
T F V V V V V T T A L T T T V V V V V V V
I E E E E E T K E E E E E E E
G D D D D D A D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
A8 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
A24 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
B4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
B13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
C7 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
C16 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
C24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 4/6 ( 66%)
Total I/O pins used: 24/53 ( 45%)
Total logic cells used: 48/576 ( 8%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 1.00/4 ( 25%)
Total fan-in: 48/2304 ( 2%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 24
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 48
Total flipflops required: 48
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 3 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 17/0
B: 0 0 0 8 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 16/0
C: 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 1 15/0
Total: 3 0 0 8 0 0 7 6 0 0 0 0 0 8 0 0 7 0 0 0 0 0 0 0 9 48/0
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
2 - - - -- INPUT G 0 0 0 0 /CLR_L
43 - - - -- INPUT G 0 0 0 0 LOCKCLK
1 - - - -- INPUT G 0 0 0 0 OUTCLK
42 - - - -- INPUT 0 0 0 1 SER_DATA
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\work\maxplus\recv\24bitshift.rpt
24bitshift
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
62 - - C -- OUTPUT 0 1 0 0 OUTD0_0
71 - - A -- OUTPUT 0 1 0 0 OUTD0_1
69 - - A -- OUTPUT 0 1 0 0 OUTD0_2
58 - - C -- OUTPUT 0 1 0 0 OUTD0_3
64 - - B -- OUTPUT 0 1 0 0 OUTD0_4
67 - - B -- OUTPUT 0 1 0 0 OUTD0_5
23 - - B -- OUTPUT 0 1 0 0 OUTD0_6
21 - - B -- OUTPUT 0 1 0 0 OUTD0_7
60 - - C -- OUTPUT 0 1 0 0 OUTD1_0
61 - - C -- OUTPUT 0 1 0 0 OUTD1_1
73 - - A -- OUTPUT 0 1 0 0 OUTD1_2
72 - - A -- OUTPUT 0 1 0 0 OUTD1_3
66 - - B -- OUTPUT 0 1 0 0 OUTD1_4
65 - - B -- OUTPUT 0 1 0 0 OUTD1_5
25 - - B -- OUTPUT 0 1 0 0 OUTD1_6
24 - - B -- OUTPUT 0 1 0 0 OUTD1_7
19 - - A -- OUTPUT 0 1 0 0 OUTFD0_0
18 - - A -- OUTPUT 0 1 0 0 OUTFD0_1
28 - - C -- OUTPUT 0 1 0 0 OUTFD0_2
30 - - C -- OUTPUT 0 1 0 0 OUTFD0_3
16 - - A -- OUTPUT 0 1 0 0 OUTFD1_0
17 - - A -- OUTPUT 0 1 0 0 OUTFD1_1
27 - - C -- OUTPUT 0 1 0 0 OUTFD1_2
29 - - C -- OUTPUT 0 1 0 0 OUTFD1_3
Code:
s = Synthesized pin or logic cell
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