📄 interleave.rpt
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Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 192
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 384
Total flipflops required: 384
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 4 6 0 0 7 0 0 0 0 0 6 0 0 0 0 8 0 7 0 7 0 0 0 0 3 8 0 0 0 0 8 0 0 0 0 7 0 71/0
B: 0 0 0 8 0 0 0 0 0 0 0 0 0 0 7 0 0 8 0 3 0 0 7 0 0 0 0 0 0 8 0 0 7 0 0 0 0 48/0
C: 0 0 0 0 0 6 0 6 0 0 8 0 0 0 0 0 0 6 0 0 0 0 8 7 0 7 0 0 0 0 0 0 0 0 0 0 0 48/0
D: 0 0 0 0 0 0 0 0 6 6 7 7 0 0 0 0 8 0 0 0 0 0 0 0 8 8 0 0 8 0 0 0 0 8 7 0 0 73/0
E: 0 0 7 0 0 0 0 0 8 0 0 7 6 8 0 0 0 0 0 0 0 0 0 0 4 0 8 8 0 0 0 0 0 0 2 8 0 66/0
F: 0 0 0 4 0 0 0 0 0 0 8 0 0 0 6 8 0 7 0 8 8 0 7 0 0 0 0 0 7 7 0 0 0 8 0 0 0 78/0
Total: 4 6 7 12 7 6 0 6 14 6 29 14 6 8 13 16 8 28 0 18 8 0 22 7 15 23 8 8 15 15 8 0 7 16 9 15 0 384/0
Device-Specific Information: e:\work\maxplus\recv\interleave.rpt
interleave
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
AE13 - - - -- INPUT G 0 0 0 0 /CLR_L
AF14 - - - -- INPUT 0 0 0 1 D0
A13 - - - -- INPUT 0 0 0 1 D1
B14 - - - -- INPUT 0 0 0 1 D2
AD5 - - - 02 INPUT 0 0 0 1 D3
B10 - - - 13 INPUT 0 0 0 1 D4
AD1 - - A -- INPUT 0 0 0 1 D5
Y26 - - - 31 INPUT 0 0 0 1 D6
C8 - - - 08 INPUT 0 0 0 1 D7
A14 - - - -- INPUT G 0 0 0 0 LOCKCLK
AF13 - - - -- INPUT G 0 0 0 0 OUTCLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\work\maxplus\recv\interleave.rpt
interleave
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
AD7 - - - 06 OUTPUT 0 1 0 0 OUTD0_0
P3 - - C -- OUTPUT 0 1 0 0 OUTD0_1
R2 - - C -- OUTPUT 0 1 0 0 OUTD0_2
R3 - - C -- OUTPUT 0 1 0 0 OUTD0_3
R22 - - C -- OUTPUT 0 1 0 0 OUTD0_4
P25 - - C -- OUTPUT 0 1 0 0 OUTD0_5
G3 - - - 08 OUTPUT 0 1 0 0 OUTD0_6
AD9 - - - 08 OUTPUT 0 1 0 0 OUTD0_7
P5 - - C -- OUTPUT 0 1 0 0 OUTD0_8
P22 - - C -- OUTPUT 0 1 0 0 OUTD0_9
R23 - - C -- OUTPUT 0 1 0 0 OUTD0_10
B5 - - - 05 OUTPUT 0 1 0 0 OUTD0_11
AA4 - - - 09 OUTPUT 0 1 0 0 OUTD1_0
C12 - - - 16 OUTPUT 0 1 0 0 OUTD1_1
E4 - - - 16 OUTPUT 0 1 0 0 OUTD1_2
C19 - - - 30 OUTPUT 0 1 0 0 OUTD1_3
B20 - - - 29 OUTPUT 0 1 0 0 OUTD1_4
AE10 - - - 12 OUTPUT 0 1 0 0 OUTD1_5
G2 - - - 02 OUTPUT 0 1 0 0 OUTD1_6
W23 - - A -- OUTPUT 0 1 0 0 OUTD1_7
A5 - - - 09 OUTPUT 0 1 0 0 OUTD1_8
AE12 - - - 17 OUTPUT 0 1 0 0 OUTD1_9
N5 - - D -- OUTPUT 0 1 0 0 OUTD1_10
AE8 - - - 09 OUTPUT 0 1 0 0 OUTD1_11
AD6 - - - 04 OUTPUT 0 1 0 0 OUTD2_0
B15 - - - 19 OUTPUT 0 1 0 0 OUTD2_1
V24 - - B -- OUTPUT 0 1 0 0 OUTD2_2
AF23 - - - 29 OUTPUT 0 1 0 0 OUTD2_3
T4 - - B -- OUTPUT 0 1 0 0 OUTD2_4
U3 - - B -- OUTPUT 0 1 0 0 OUTD2_5
AD19 - - - 31 OUTPUT 0 1 0 0 OUTD2_6
U23 - - B -- OUTPUT 0 1 0 0 OUTD2_7
V25 - - B -- OUTPUT 0 1 0 0 OUTD2_8
B11 - - - 15 OUTPUT 0 1 0 0 OUTD2_9
T2 - - B -- OUTPUT 0 1 0 0 OUTD2_10
U2 - - B -- OUTPUT 0 1 0 0 OUTD2_11
A6 - - - 12 OUTPUT 0 1 0 0 OUTD3_0
B9 - - - 11 OUTPUT 0 1 0 0 OUTD3_1
AF12 - - - 18 OUTPUT 0 1 0 0 OUTD3_2
H4 - - F -- OUTPUT 0 1 0 0 OUTD3_3
E23 - - F -- OUTPUT 0 1 0 0 OUTD3_4
J24 - - F -- OUTPUT 0 1 0 0 OUTD3_5
F22 - - F -- OUTPUT 0 1 0 0 OUTD3_6
AE24 - - - 34 OUTPUT 0 1 0 0 OUTD3_7
AD12 - - - 16 OUTPUT 0 1 0 0 OUTD3_8
H2 - - F -- OUTPUT 0 1 0 0 OUTD3_9
H3 - - F -- OUTPUT 0 1 0 0 OUTD3_10
J2 - - F -- OUTPUT 0 1 0 0 OUTD3_11
AB2 - - - 11 OUTPUT 0 1 0 0 OUTD4_0
M2 - - D -- OUTPUT 0 1 0 0 OUTD4_1
M4 - - D -- OUTPUT 0 1 0 0 OUTD4_2
M25 - - D -- OUTPUT 0 1 0 0 OUTD4_3
B23 - - - 33 OUTPUT 0 1 0 0 OUTD4_4
P26 - - D -- OUTPUT 0 1 0 0 OUTD4_5
F3 - - - 12 OUTPUT 0 1 0 0 OUTD4_6
M3 - - D -- OUTPUT 0 1 0 0 OUTD4_7
W5 - - A -- OUTPUT 0 1 0 0 OUTD4_8
Y5 - - A -- OUTPUT 0 1 0 0 OUTD4_9
AA2 - - - 05 OUTPUT 0 1 0 0 OUTD4_10
AC4 - - A -- OUTPUT 0 1 0 0 OUTD4_11
Y22 - - A -- OUTPUT 0 1 0 0 OUTD5_0
AD16 - - - 24 OUTPUT 0 1 0 0 OUTD5_1
B19 - - - 27 OUTPUT 0 1 0 0 OUTD5_2
F24 - - - 28 OUTPUT 0 1 0 0 OUTD5_3
B17 - - - 23 OUTPUT 0 1 0 0 OUTD5_4
C16 - - - 23 OUTPUT 0 1 0 0 OUTD5_5
Y24 - - - 33 OUTPUT 0 1 0 0 OUTD5_6
M24 - - D -- OUTPUT 0 1 0 0 OUTD5_7
AA24 - - A -- OUTPUT 0 1 0 0 OUTD5_8
C24 - - - 36 OUTPUT 0 1 0 0 OUTD5_9
AA22 - - A -- OUTPUT 0 1 0 0 OUTD5_10
AF20 - - - 25 OUTPUT 0 1 0 0 OUTD5_11
AA25 - - - 27 OUTPUT 0 1 0 0 OUTD6_0
C18 - - - 28 OUTPUT 0 1 0 0 OUTD6_1
J4 - - F -- OUTPUT 0 1 0 0 OUTD6_2
A15 - - - 19 OUTPUT 0 1 0 0 OUTD6_3
G22 - - F -- OUTPUT 0 1 0 0 OUTD6_4
K24 - - F -- OUTPUT 0 1 0 0 OUTD6_5
A18 - - - 22 OUTPUT 0 1 0 0 OUTD6_6
AE16 - - - 22 OUTPUT 0 1 0 0 OUTD6_7
L23 - - E -- OUTPUT 0 1 0 0 OUTD6_8
L25 - - E -- OUTPUT 0 1 0 0 OUTD6_9
A19 - - - 24 OUTPUT 0 1 0 0 OUTD6_10
AF9 - - - 14 OUTPUT 0 1 0 0 OUTD6_11
C22 - - - 35 OUTPUT 0 1 0 0 OUTD7_0
C23 - - - 35 OUTPUT 0 1 0 0 OUTD7_1
AF5 - - - 10 OUTPUT 0 1 0 0 OUTD7_2
AD10 - - - 10 OUTPUT 0 1 0 0 OUTD7_3
K4 - - E -- OUTPUT 0 1 0 0 OUTD7_4
L3 - - E -- OUTPUT 0 1 0 0 OUTD7_5
A8 - - - 14 OUTPUT 0 1 0 0 OUTD7_6
L2 - - E -- OUTPUT 0 1 0 0 OUTD7_7
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