📄 interleave.rpt
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A2 GNDINT C22 OUTD7_0 K24 OUTD6_5 U26 GNDINT AD12 OUTD3_8
A3 OUTD12_11 C23 OUTD7_1 K25 N.C. V1 N.C. AD13 RESERVED
A4 RESERVED C24 OUTD5_9 K26 OUTD14_11 V2 VCCIO AD14 GNDINT
A5 OUTD1_8 C25 GNDINT L1 OUTD7_10 V3 N.C. AD15 RESERVED
A6 OUTD3_0 C26 VCCINT L2 OUTD7_7 V4 N.C. AD16 OUTD5_1
A7 VCCIO D1 N.C. L3 OUTD7_5 V5 OUTD12_8 AD17 RESERVED
A8 OUTD7_6 D2 ^nCONFIG L4 OUTD15_3 V22 OUTD10_9 AD18 VCCIO
A9 OUTD11_0 D3 ^MSEL1 L5 OUTD15_4 V23 OUTD10_7 AD19 OUTD2_6
A10 GNDINT D4 ^MSEL0 L22 OUTD14_9 V24 OUTD2_2 AD20 GNDINT
A11 OUTD11_3 D5 VCCINT L23 OUTD6_8 V25 OUTD2_8 AD21 OUTD12_4
A12 OUTD12_9 D22 #TMS L24 OUTD7_11 V26 N.C. AD22 RESERVED
A13 D1 D23 #TRST L25 OUTD6_9 W1 GNDINT AD23 OUTD15_1
A14 LOCKCLK D24 ^nSTATUS L26 OUTD11_10 W2 N.C. AD24 RESERVED
A15 OUTD6_3 D25 VCCIO M1 GNDINT W3 N.C. AD25 #TCK
A16 OUTD14_2 D26 N.C. M2 OUTD4_1 W4 OUTD9_1 AD26 VCCINT
A17 RESERVED E1 N.C. M3 OUTD4_7 W5 OUTD4_8 AE1 GNDINT
A18 OUTD6_6 E2 N.C. M4 OUTD4_2 W22 VCCIO AE2 GNDINT
A19 OUTD6_10 E3 OUTD8_9 M5 OUTD9_11 W23 OUTD1_7 AE3 RESERVED
A20 GNDINT E4 OUTD1_2 M22 OUTD13_5 W24 OUTD13_0 AE4 OUTD10_1
A21 RESERVED E5 RESERVED M23 VCCIO W25 OUTD13_10 AE5 OUTD8_0
A22 OUTD13_3 E22 OUTD14_6 M24 OUTD5_7 W26 OUTD10_6 AE6 RESERVED
A23 VCCIO E23 OUTD3_4 M25 OUTD4_3 Y1 N.C. AE7 GNDINT
A24 OUTD10_2 E24 OUTD14_4 M26 VCCINT Y2 N.C. AE8 OUTD1_11
A25 RESERVED E25 RESERVED N1 VCCINT Y3 RESERVED AE9 OUTD11_1
A26 VCCINT E26 OUTD14_10 N2 OUTD9_10 Y4 OUTD9_7 AE10 OUTD1_5
B1 GNDINT F1 VCCINT N3 OUTD12_6 Y5 OUTD4_9 AE11 OUTD11_11
B2 RESERVED F2 OUTD9_9 N4 OUTD12_7 Y22 OUTD5_0 AE12 OUTD1_9
B3 OUTD15_9 F3 OUTD4_6 N5 OUTD1_10 Y23 N.C. AE13 /CLR_L
B4 VCCIO F4 VCCIO N22 OUTD13_6 Y24 OUTD5_6 AE14 OUTD14_3
B5 OUTD0_11 F5 RESERVED N23 OUTD12_5 Y25 OUTD15_0 AE15 OUTD14_5
B6 RESERVED F22 OUTD3_6 N24 OUTD13_4 Y26 D6 AE16 OUTD6_7
B7 OUTD9_0 F23 OUTD9_3 N25 RESERVED AA1 VCCINT AE17 RESERVED
B8 OUTD9_8 F24 OUTD5_3 N26 GNDINT AA2 OUTD4_10 AE18 RESERVED
B9 OUTD3_1 F25 OUTD13_1 P1 OUTD8_2 AA3 OUTD8_7 AE19 OUTD13_2
B10 D4 F26 RESERVED P2 VCCIO AA4 OUTD1_0 AE20 OUTD11_5
B11 OUTD2_9 G1 N.C. P3 OUTD0_1 AA5 OUTD9_2 AE21 RESERVED
B12 RESERVED G2 OUTD1_6 P4 OUTD8_8 AA22 OUTD5_10 AE22 RESERVED
B13 GNDINT G3 OUTD0_6 P5 OUTD0_8 AA23 OUTD13_11 AE23 OUTD13_7
B14 D2 G4 OUTD10_0 P22 OUTD0_9 AA24 OUTD5_8 AE24 OUTD3_7
B15 OUTD2_1 G5 N.C. P23 OUTD8_4 AA25 OUTD6_0 AE25 GNDINT
B16 OUTD14_7 G22 OUTD6_4 P24 N.C. AA26 OUTD9_4 AE26 GNDINT
B17 OUTD5_4 G23 N.C. P25 OUTD0_5 AB1 VCCIO AF1 VCCINT
B18 OUTD14_8 G24 RESERVED P26 OUTD4_5 AB2 OUTD4_0 AF2 RESERVED
B19 OUTD5_2 G25 RESERVED R1 GNDINT AB3 OUTD15_6 AF3 VCCIO
B20 OUTD1_4 G26 N.C. R2 OUTD0_2 AB4 OUTD11_9 AF4 RESERVED
B21 RESERVED H1 N.C. R3 OUTD0_3 AB5 OUTD12_0 AF5 OUTD7_2
B22 GNDINT H2 OUTD3_9 R4 OUTD9_6 AB22 OUTD13_9 AF6 OUTD12_1
B23 OUTD4_4 H3 OUTD3_10 R5 OUTD8_1 AB23 OUTD8_6 AF7 VCCIO
B24 OUTD11_6 H4 OUTD3_3 R22 OUTD0_4 AB24 RESERVED AF8 RESERVED
B25 GNDINT H5 OUTD11_2 R23 OUTD0_10 AB25 RESERVED AF9 OUTD6_11
B26 GNDINT H22 VCCINT R24 N.C. AB26 OUTD12_3 AF10 RESERVED
C1 N.C. H23 GNDINT R25 OUTD8_11 AC1 OUTD12_10 AF11 GNDINT
C2 GNDINT H24 VCCIO R26 GNDINT AC2 ^nCE AF12 OUTD3_2
C3 RESERVED H25 N.C. T1 GNDINT AC3 #TDI AF13 OUTCLK
C4 RESERVED H26 N.C. T2 OUTD2_10 AC4 OUTD4_11 AF14 D0
C5 RESERVED J1 VCCINT T3 OUTD10_10 AC5 ^DCLK AF15 OUTD13_8
C6 OUTD15_8 J2 OUTD3_11 T4 OUTD2_4 AC22 ^nCEO AF16 VCCIO
C7 RESERVED J3 OUTD9_5 T5 OUTD10_11 AC23 #TDO AF17 RESERVED
C8 D7 J4 OUTD6_2 T22 OUTD10_8 AC24 ^CONF_DONEAF18 OUTD8_5
C9 GNDINT J5 OUTD11_8 T23 N.C. AC25 VCCIO AF19 GNDINT
C10 OUTD15_5 J22 OUTD11_4 T24 OUTD8_3 AC26 N.C. AF20 OUTD5_11
C11 RESERVED J23 OUTD14_1 T25 VCCIO AD1 D5 AF21 OUTD15_11
C12 OUTD1_1 J24 OUTD3_5 T26 VCCINT AD2 GNDINT AF22 OUTD15_10
C13 GNDINT J25 N.C. U1 OUTD10_5 AD3 ^DATA0 AF23 OUTD2_3
C14 VCCINT J26 GNDINT U2 OUTD2_11 AD4 RESERVED AF24 RESERVED
C15 VCCIO K1 GNDINT U3 OUTD2_5 AD5 D3 AF25 GNDINT
C16 OUTD5_5 K2 OUTD15_2 U4 OUTD10_4 AD6 OUTD2_0 AF26 VCCINT
C17 OUTD12_2 K3 OUTD14_0 U5 VCCINT AD7 OUTD0_0
C18 OUTD6_1 K4 OUTD7_4 U22 OUTD8_10 AD8 RESERVED
C19 OUTD1_3 K5 VCCIO U23 OUTD2_7 AD9 OUTD0_7
C20 RESERVED K22 OUTD7_8 U24 OUTD10_3 AD10 OUTD7_3
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\work\maxplus\recv\interleave.rpt
interleave
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
A2 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
A5 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
A11 6/ 8( 75%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
A16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
A18 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
A19 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
A24 3/ 8( 37%) 2/ 8( 25%) 0/ 8( 0%) 2/2 1/2 1/22( 4%)
A25 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
A30 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
A35 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
B4 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
B15 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
B18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
B19 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
B22 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
B29 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
B32 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
C6 6/ 8( 75%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
C8 6/ 8( 75%) 3/ 8( 37%) 0/ 8( 0%) 2/2 1/2 1/22( 4%)
C11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
C18 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
C22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
C23 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
C25 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
D9 6/ 8( 75%) 4/ 8( 50%) 0/ 8( 0%) 2/2 1/2 1/22( 4%)
D10 6/ 8( 75%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
D11 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D12 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
D17 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
D24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D25 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D28 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
D33 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
D34 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
E3 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
E9 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
E12 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
E13 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
E14 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
E24 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
E26 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
E27 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
E34 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
E35 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
F4 4/ 8( 50%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
F11 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
F15 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
F16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
F18 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
F19 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
F20 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 1/22( 4%)
F22 7/ 8( 87%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
F28 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
F29 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
F33 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 197/240 ( 82%)
Total logic cells used: 384/1728 ( 22%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 1.00/4 ( 25%)
Total fan-in: 384/6912 ( 5%)
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