📄 recv.rpt
字号:
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|a_fefifo:fifo_state|lpm_counter:59|lpm_add_sub:add_sub|altshift:result_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|a_fefifo:fifo_state|lpm_counter:59|lpm_add_sub:add_sub|altshift:carry_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|a_fefifo:fifo_state|lpm_counter:59|lpm_add_sub:add_sub|altshift:oflow_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|a_fefifo:fifo_state|lpm_counter:59|lpm_constant:scdw|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|lpm_add_sub:344|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|lpm_add_sub:344|addcore:adder|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|lpm_add_sub:344|altshift:result_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|lpm_add_sub:344|altshift:carry_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|lpm_add_sub:344|altshift:oflow_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:375|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|altshift:external_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|muxlut:72|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|muxlut:87|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|muxlut:102|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|muxlut:117|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|muxlut:132|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|muxlut:147|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:411|lpm_mux:49|muxlut:162|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:435|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|altshift:external_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|muxlut:72|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|muxlut:87|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|muxlut:102|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|muxlut:117|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|muxlut:132|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|muxlut:147|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|busmux:471|lpm_mux:49|muxlut:162|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:495|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:507|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:519|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:559|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:572|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:586|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|dffpipe:618|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|lpm_or:632|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:59|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:85|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:111|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:137|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF1|lpm_ff:163|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF2|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF2|lpm_ff:59|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF2|lpm_ff:85|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF2|lpm_ff:111|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF2|lpm_ff:137|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_f2fifo:FF2|lpm_ff:163|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:59|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:59|lpm_add_sub:add_sub|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:59|lpm_add_sub:add_sub|addcore:adder|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:59|lpm_add_sub:add_sub|altshift:result_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:59|lpm_add_sub:add_sub|altshift:carry_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:59|lpm_add_sub:add_sub|altshift:oflow_ext_latency_ffs|
|lpm_fifo:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|lpm_counter:59|lpm_constant:scdw|
Device-Specific Information: e:\aa2\recv\recv.rpt
recv
***** Logic for device 'recv' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R
E E E E E E E E E E E E
S S S S S G G G G V S S S S S S S
E E E E G V G E N N N N C E E V E E E E E
R R R R F N C N R D D D D C R R C R R R R R
V V V V L D C D V I I I I I V D D D / / V C V V V V d V
E E E E A I D D D D I D D D D I E N N N N N E 1 1 1 R W E I E E E E d E
D D D D G O 7 6 5 4 O 3 2 1 0 O D T T T T T D 5 4 3 D R D O D D D D 1 D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
dd10 | 12 97 | RESERVED
dd6 | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
dd8 | 17 92 | dd11
RESERVED | 18 91 | dd5
RESERVED | 19 EPF10K20TC144-3 90 | dd3
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | dd0
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
d R R G d R R R V R C R R G / V V G C G G G R d V R R R R G d R R R V R
d E E N d E E E C E / E E N c C C N L N N N E d C E E E E N d E E E C E
9 S S D 4 S S S C S D S S D s C C D K D D D S 2 C S S S S D 7 S S S C S
E E I E E E I E E E I 1 I I I I I I E I E E E E I E E E I E
R R O R R R O R R R O N N N N N N R O R R R R O R R R O R
V V V V V V V V T T T T T T V V V V V V V V V
E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\aa2\recv\recv.rpt
recv
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 7/22( 31%)
A3 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 10/22( 45%)
A4 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
A7 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 7/22( 31%)
A8 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 8/22( 36%)
A10 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
A11 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
A13 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A14 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 8/22( 36%)
A15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 2/2 2/22( 9%)
A16 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 8/22( 36%)
A17 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
A18 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
A19 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 2/2 1/2 11/22( 50%)
A20 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
A21 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 1/2 2/22( 9%)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -