recv.rpt

在Maxplus软件平台开发的

Project Information                                       e:\aa2\recv\recv.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 01/07/2003 16:09:46

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

recv      EPF10K20TC144-3  6      15     8    2048      16 %    858      74 %

User Pins:                 6      15     8  



Project Information                                       e:\aa2\recv\recv.rpt

** PROJECT COMPILATION MESSAGES **

Warning: No Clock transition on flipflop ':98'


Project Information                                       e:\aa2\recv\recv.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

recv@47                           C/D
recv@55                           CLK
recv@51                           /cs1
recv@130                          D0
recv@131                          D1
recv@132                          D2
recv@133                          D3
recv@135                          D4
recv@136                          D5
recv@137                          D6
recv@138                          D7
recv@119                          D13
recv@120                          D14
recv@121                          D15
recv@140                          FLAG
recv@118                          /RD
recv@117                          /WR


Project Information                                       e:\aa2\recv\recv.rpt

** STATE MACHINE ASSIGNMENTS **


|LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|IM_FEEDS_WHO: MACHINE
        OF BITS (
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|b_im_mux,
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|b_im_feeds
        )
        WITH STATES (
                    im_feeds_ff1 = B"00", 
                 im_feeds_ff1_da = B"10", 
                    im_feeds_ff2 = B"01", 
                 im_feeds_ff2_da = B"11"
);


|LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|READ_WHERE: MACHINE
        OF BITS (
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|b_readside
        )
        WITH STATES (
                        read_ff1 = B"0", 
                        read_ff2 = B"1"
);


|LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|WRITE_WHERE: MACHINE
        OF BITS (
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|b_writeside
        )
        WITH STATES (
                       write_ff1 = B"0", 
                       write_ff2 = B"1"
);


|LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|a_fefifo:fifo_state|sm_emptyfull: MACHINE
        OF BITS (
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|a_fefifo:fifo_state|b_full,
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|a_fefifo:fifo_state|b_non_empty
        )
        WITH STATES (
                     state_empty = B"00", 
                    state_middle = B"01", 
                      state_full = B"11"
);


|LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|sm_emptyfull: MACHINE
        OF BITS (
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_full,
           |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_fefifo:FEF|b_non_empty
        )
        WITH STATES (
                     state_empty = B"00", 
                    state_middle = B"01", 
                      state_full = B"11"
);



Project Information                                       e:\aa2\recv\recv.rpt

** EMBEDDED ARRAYS **


|LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|content: MEMORY (
               width        =    8;
               depth        =  128;
               segmentsize  =  128;
               mode         = MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1;
         )
         OF SEGMENTS (
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_7,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_6,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_5,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_4,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_3,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_2,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_1,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block0|segment0_0
);



|LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|content: MEMORY (
               width        =    8;
               depth        =  128;
               segmentsize  =  128;
               mode         = MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1;
         )
         OF SEGMENTS (
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_7,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_6,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_5,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_4,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_3,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_2,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_1,
               |LPM_FIFO:24|scfifo:myFIFO|a_i2fifo:subfifo|a_imfifo:IMF|altram:memory_block1|segment0_0
);




Project Information                                       e:\aa2\recv\recv.rpt