📄 rfec.rpt
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EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\work\20\recv\rfec.rpt
rfec
** EQUATIONS **
DI0 : INPUT;
DI1 : INPUT;
DI2 : INPUT;
DI3 : INPUT;
DI4 : INPUT;
DI5 : INPUT;
DI6 : INPUT;
DI7 : INPUT;
DI8 : INPUT;
DI9 : INPUT;
DI10 : INPUT;
DI11 : INPUT;
-- Node name is 'DO0'
-- Equation name is 'DO0', type is output
DO0 = _LC2_A3;
-- Node name is 'DO1'
-- Equation name is 'DO1', type is output
DO1 = _LC5_A6;
-- Node name is 'DO2'
-- Equation name is 'DO2', type is output
DO2 = _LC7_A3;
-- Node name is 'DO3'
-- Equation name is 'DO3', type is output
DO3 = _LC3_A6;
-- Node name is 'DO4'
-- Equation name is 'DO4', type is output
DO4 = _LC6_A6;
-- Node name is 'DO5'
-- Equation name is 'DO5', type is output
DO5 = _LC4_A6;
-- Node name is 'DO6'
-- Equation name is 'DO6', type is output
DO6 = _LC3_A3;
-- Node name is 'DO7'
-- Equation name is 'DO7', type is output
DO7 = _LC8_A6;
-- Node name is '|rfecpre:68|12and:29|:60' = '|rfecpre:68|12and:29|output'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ001);
_EQ001 = DI4 & !DI5 & DI6 & _LC3_A12
# DI4 & DI5 & DI6 & !_LC3_A12
# !DI4 & !DI5 & !DI6 & _LC3_A12
# !DI4 & DI5 & !DI6 & !_LC3_A12
# DI4 & DI5 & !DI6 & _LC3_A12
# DI4 & !DI5 & !DI6 & !_LC3_A12
# !DI4 & DI5 & DI6 & _LC3_A12
# !DI4 & !DI5 & DI6 & !_LC3_A12;
-- Node name is '|rfecpre:68|12and:29|~60~1' = '|rfecpre:68|12and:29|output~1'
-- Equation name is '_LC3_A12', type is buried
-- synthesized logic cell
_LC3_A12 = LCELL( _EQ002);
_EQ002 = !DI0 & !DI2 & DI8
# DI0 & !DI2 & !DI8
# DI0 & DI2 & DI8
# !DI0 & DI2 & !DI8;
-- Node name is '|rfecpre:68|12and:30|:60' = '|rfecpre:68|12and:30|output'
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ003);
_EQ003 = !DI4 & DI5 & DI7 & _LC2_A12
# DI4 & DI5 & DI7 & !_LC2_A12
# !DI4 & !DI5 & !DI7 & _LC2_A12
# DI4 & !DI5 & !DI7 & !_LC2_A12
# DI4 & !DI5 & DI7 & _LC2_A12
# !DI4 & !DI5 & DI7 & !_LC2_A12
# DI4 & DI5 & !DI7 & _LC2_A12
# !DI4 & DI5 & !DI7 & !_LC2_A12;
-- Node name is '|rfecpre:68|12and:30|~60~1' = '|rfecpre:68|12and:30|output~1'
-- Equation name is '_LC2_A12', type is buried
-- synthesized logic cell
_LC2_A12 = LCELL( _EQ004);
_EQ004 = !DI1 & !DI3 & DI9
# DI1 & !DI3 & !DI9
# DI1 & DI3 & DI9
# !DI1 & DI3 & !DI9;
-- Node name is '|rfecpre:68|12and:31|:60' = '|rfecpre:68|12and:31|output'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ005);
_EQ005 = DI4 & !DI6 & !DI7 & !_LC7_A6
# !DI4 & !DI6 & !DI7 & _LC7_A6
# DI4 & !DI6 & DI7 & _LC7_A6
# !DI4 & !DI6 & DI7 & !_LC7_A6
# DI4 & DI6 & DI7 & !_LC7_A6
# !DI4 & DI6 & DI7 & _LC7_A6
# DI4 & DI6 & !DI7 & _LC7_A6
# !DI4 & DI6 & !DI7 & !_LC7_A6;
-- Node name is '|rfecpre:68|12and:31|~60~1' = '|rfecpre:68|12and:31|output~1'
-- Equation name is '_LC7_A6', type is buried
-- synthesized logic cell
_LC7_A6 = LCELL( _EQ006);
_EQ006 = DI0 & DI1 & DI10
# !DI0 & DI1 & !DI10
# DI0 & !DI1 & !DI10
# !DI0 & !DI1 & DI10;
-- Node name is '|rfecpre:68|12and:32|:60' = '|rfecpre:68|12and:32|output'
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = LCELL( _EQ007);
_EQ007 = DI5 & DI6 & DI7 & !_LC1_A12
# !DI5 & DI6 & DI7 & _LC1_A12
# DI5 & DI6 & !DI7 & _LC1_A12
# !DI5 & DI6 & !DI7 & !_LC1_A12
# DI5 & !DI6 & DI7 & _LC1_A12
# !DI5 & !DI6 & DI7 & !_LC1_A12
# DI5 & !DI6 & !DI7 & !_LC1_A12
# !DI5 & !DI6 & !DI7 & _LC1_A12;
-- Node name is '|rfecpre:68|12and:32|~60~1' = '|rfecpre:68|12and:32|output~1'
-- Equation name is '_LC1_A12', type is buried
-- synthesized logic cell
_LC1_A12 = LCELL( _EQ008);
_EQ008 = DI2 & DI3 & DI11
# !DI2 & DI3 & !DI11
# DI2 & !DI3 & !DI11
# !DI2 & !DI3 & DI11;
-- Node name is '|74138:63|~22~1' = '|74138:63|Y7N~1'
-- Equation name is '_LC8_A3', type is buried
-- synthesized logic cell
_LC8_A3 = LCELL( _EQ009);
_EQ009 = !_LC1_A6
# _LC6_A3
# !_LC4_A3;
-- Node name is '|74138:64|~16~1' = '|74138:64|Y1N~1'
-- Equation name is '_LC5_A3', type is buried
-- synthesized logic cell
_LC5_A3 = LCELL( _EQ010);
_EQ010 = !_LC2_A6
# _LC4_A3;
-- Node name is '|74138:64|~21~1' = '|74138:64|Y6N~1'
-- Equation name is '_LC1_A3', type is buried
-- synthesized logic cell
_LC1_A3 = LCELL( _EQ011);
_EQ011 = !_LC4_A3
# !_LC6_A3;
-- Node name is ':75'
-- Equation name is '_LC3_A3', type is buried
!_LC3_A3 = _LC3_A3~NOT;
_LC3_A3~NOT = LCELL( _EQ012);
_EQ012 = !DI6 & _LC5_A3
# !DI6 & !_LC6_A3
# !DI6 & !_LC1_A6
# DI6 & _LC1_A6 & !_LC5_A3 & _LC6_A3;
-- Node name is ':76'
-- Equation name is '_LC4_A6', type is buried
!_LC4_A6 = _LC4_A6~NOT;
_LC4_A6~NOT = LCELL( _EQ013);
_EQ013 = !DI5 & _LC1_A3
# !DI5 & _LC1_A6
# !DI5 & !_LC2_A6
# DI5 & !_LC1_A3 & !_LC1_A6 & _LC2_A6;
-- Node name is ':77'
-- Equation name is '_LC8_A6', type is buried
!_LC8_A6 = _LC8_A6~NOT;
_LC8_A6~NOT = LCELL( _EQ014);
_EQ014 = !DI7 & _LC2_A6
# !DI7 & !_LC1_A6
# !DI7 & _LC1_A3
# DI7 & !_LC1_A3 & _LC1_A6 & !_LC2_A6;
-- Node name is ':78'
-- Equation name is '_LC6_A6', type is buried
!_LC6_A6 = _LC6_A6~NOT;
_LC6_A6~NOT = LCELL( _EQ015);
_EQ015 = !DI4 & _LC8_A3
# !DI4 & !_LC2_A6
# DI4 & _LC2_A6 & !_LC8_A3;
-- Node name is ':79'
-- Equation name is '_LC3_A6', type is buried
!_LC3_A6 = _LC3_A6~NOT;
_LC3_A6~NOT = LCELL( _EQ016);
_EQ016 = !DI3 & _LC1_A3
# !DI3 & _LC1_A6
# !DI3 & _LC2_A6
# DI3 & !_LC1_A3 & !_LC1_A6 & !_LC2_A6;
-- Node name is ':80'
-- Equation name is '_LC7_A3', type is buried
!_LC7_A3 = _LC7_A3~NOT;
_LC7_A3~NOT = LCELL( _EQ017);
_EQ017 = !DI2 & _LC5_A3
# !DI2 & !_LC6_A3
# !DI2 & _LC1_A6
# DI2 & !_LC1_A6 & !_LC5_A3 & _LC6_A3;
-- Node name is ':81'
-- Equation name is '_LC5_A6', type is buried
!_LC5_A6 = _LC5_A6~NOT;
_LC5_A6~NOT = LCELL( _EQ018);
_EQ018 = !DI1 & _LC8_A3
# !DI1 & _LC2_A6
# DI1 & !_LC2_A6 & !_LC8_A3;
-- Node name is ':82'
-- Equation name is '_LC2_A3', type is buried
!_LC2_A3 = _LC2_A3~NOT;
_LC2_A3~NOT = LCELL( _EQ019);
_EQ019 = !DI0 & _LC5_A3
# !DI0 & !_LC1_A6
# !DI0 & _LC6_A3
# DI0 & _LC1_A6 & !_LC5_A3 & !_LC6_A3;
Project Information e:\work\20\recv\rfec.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,233K
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