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📄 testfifo.rpt

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         # !_LC4_B11 &  _LC7_B11
         #  _LC2_B9 &  _LC4_B11 &  _LC5_B11 & !_LC7_B11
         # !_LC2_B9 &  _LC7_B11;

-- Node name is '|CSFIFO:1|lpm_counter:rd_ptr|dffs6' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC3_B11', type is buried 
_LC3_B11 = DFFE( _EQ038, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ038 =  _LC3_B11 & !_LC8_B11
         #  _LC2_B9 & !_LC3_B11 &  _LC8_B11
         # !_LC2_B9 &  _LC3_B11;

-- Node name is '|CSFIFO:1|lpm_counter:rd_ptr|dffs7' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = DFFE( _EQ039, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ039 = !_LC3_B11 &  _LC6_B11
         #  _LC6_B11 & !_LC8_B11
         #  _LC2_B9 &  _LC3_B11 & !_LC6_B11 &  _LC8_B11
         # !_LC2_B9 &  _LC6_B11;

-- Node name is '|CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B9', type is buried 
_LC4_B9  = LCELL( _EQ040);
  _EQ040 =  _LC3_B9 &  _LC7_B9 &  _LC8_B9;

-- Node name is '|CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B11', type is buried 
_LC5_B11 = LCELL( _EQ041);
  _EQ041 =  _LC2_B11 &  _LC4_B9;

-- Node name is '|CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B11', type is buried 
_LC8_B11 = LCELL( _EQ042);
  _EQ042 =  _LC2_B11 &  _LC4_B9 &  _LC4_B11 &  _LC7_B11;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs0' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = DFFE( _EQ043, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ043 =  _LC1_B7 &  _LC5_B2
         #  _LC5_B2 & !WR
         # !_LC1_B7 & !_LC5_B2 &  WR;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs1' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = DFFE( _EQ044, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ044 =  _LC5_B2 &  _LC6_B2 & !_LC8_B2
         # !_LC5_B2 &  _LC8_B2
         # !_LC6_B2 &  _LC8_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs2' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = DFFE( _EQ045, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ045 =  _LC2_B5 & !_LC5_B2
         #  _LC2_B5 & !_LC8_B2
         # !_LC2_B5 &  _LC5_B2 &  _LC6_B2 &  _LC8_B2
         #  _LC2_B5 & !_LC6_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs3' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = DFFE( _EQ046, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ046 =  _LC4_B1 & !_LC6_B1
         # !_LC4_B1 &  _LC6_B1 &  _LC6_B2
         #  _LC4_B1 & !_LC6_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs4' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = DFFE( _EQ047, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ047 =  _LC2_B1 & !_LC4_B1
         #  _LC2_B1 & !_LC6_B1
         # !_LC2_B1 &  _LC4_B1 &  _LC6_B1 &  _LC6_B2
         #  _LC2_B1 & !_LC6_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs5' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC3_B1', type is buried 
_LC3_B1  = DFFE( _EQ048, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ048 =  _LC3_B1 & !_LC7_B1
         # !_LC2_B1 &  _LC3_B1
         #  _LC2_B1 & !_LC3_B1 &  _LC6_B2 &  _LC7_B1
         #  _LC3_B1 & !_LC6_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs6' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = DFFE( _EQ049, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ049 =  _LC1_B4 & !_LC8_B1
         # !_LC1_B4 &  _LC6_B2 &  _LC8_B1
         #  _LC1_B4 & !_LC6_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|dffs7' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = DFFE( _EQ050, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ050 = !_LC1_B4 &  _LC4_B4
         #  _LC4_B4 & !_LC8_B1
         #  _LC1_B4 & !_LC4_B4 &  _LC6_B2 &  _LC8_B1
         #  _LC4_B4 & !_LC6_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B1', type is buried 
_LC6_B1  = LCELL( _EQ051);
  _EQ051 =  _LC2_B5 &  _LC5_B2 &  _LC8_B2;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B1', type is buried 
_LC7_B1  = LCELL( _EQ052);
  _EQ052 =  _LC4_B1 &  _LC6_B1;

-- Node name is '|CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B1', type is buried 
_LC8_B1  = LCELL( _EQ053);
  _EQ053 =  _LC2_B1 &  _LC3_B1 &  _LC4_B1 &  _LC6_B1;

-- Node name is '|CSFIFO:1|rd_out0' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC7_B20', type is buried 
_LC7_B20 = DFFE( _EC6_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|rd_out1' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = DFFE( _EC3_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|rd_out2' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC6_B9', type is buried 
_LC6_B9  = DFFE( _EC2_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|rd_out3' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC2_B20', type is buried 
_LC2_B20 = DFFE( _EC5_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|rd_out4' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC3_B20', type is buried 
_LC3_B20 = DFFE( _EC8_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|rd_out5' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC6_B20', type is buried 
_LC6_B20 = DFFE( _EC7_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|rd_out6' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC4_B20', type is buried 
_LC4_B20 = DFFE( _EC1_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|rd_out7' from file "csfifo.tdf" line 84, column 9
-- Equation name is '_LC5_B20', type is buried 
_LC5_B20 = DFFE( _EC4_B, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  _LC1_B9);

-- Node name is '|CSFIFO:1|valid_rreq' from file "csfifo.tdf" line 150, column 21
-- Equation name is '_LC2_B9', type is buried 
!_LC2_B9 = _LC2_B9~NOT;
_LC2_B9~NOT = LCELL( _EQ054);
  _EQ054 = !_LC5_B7
         # !RD;

-- Node name is '|CSFIFO:1|valid_wreq' from file "csfifo.tdf" line 159, column 22
-- Equation name is '_LC6_B2', type is buried 
!_LC6_B2 = _LC6_B2~NOT;
_LC6_B2~NOT = LCELL( _EQ055);
  _EQ055 =  _LC1_B7
         # !WR;

-- Node name is '|CSFIFO:1|:312' from file "csfifo.tdf" line 180, column 48
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ056);
  _EQ056 = !_LC1_B7 & !_LC8_B10 &  WR;

-- Node name is '|CSFIFO:1|:314' from file "csfifo.tdf" line 184, column 52
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = LCELL( _EQ057);
  _EQ057 =  _LC5_B7 & !_LC8_B10 &  RD;

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC6_B', type is memory 
_EC6_B   = MEMORY_SEGMENT( INDATA0, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_B', type is memory 
_EC3_B   = MEMORY_SEGMENT( INDATA1, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_B', type is memory 
_EC2_B   = MEMORY_SEGMENT( INDATA2, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC5_B', type is memory 
_EC5_B   = MEMORY_SEGMENT( INDATA3, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_4' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC8_B', type is memory 
_EC8_B   = MEMORY_SEGMENT( INDATA4, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_5' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC7_B', type is memory 
_EC7_B   = MEMORY_SEGMENT( INDATA5, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_6' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_B', type is memory 
_EC1_B   = MEMORY_SEGMENT( INDATA6, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);

-- Node name is '|CSFIFO:1|altram:ram_block|segment0_7' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_B', type is memory 
_EC4_B   = MEMORY_SEGMENT( INDATA7, GLOBAL( CLK), VCC, _LC3_B2, VCC, _LC1_B2, _LC5_B9, _LC3_B10, _LC1_B11, _LC1_B10, _LC5_B1, _LC6_B4, _LC2_B4, VCC, VCC, VCC,);



Project Information                      d:\maxplus\max2work\tran\testfifo.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,010K

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