📄 testfifo.rpt
字号:
5 - - - 05 INPUT 0 0 0 1 INDATA7
44 - - - -- INPUT 0 0 0 6 RD
42 - - - -- INPUT 0 0 0 5 WR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus\max2work\tran\testfifo.rpt
testfifo
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
70 - - A -- OUTPUT 0 1 0 0 EMPTY
21 - - B -- OUTPUT 0 1 0 0 FULL
53 - - - 20 OUTPUT 0 1 0 0 Q0
22 - - B -- OUTPUT 0 1 0 0 Q1
38 - - - 10 OUTPUT 0 1 0 0 Q2
72 - - A -- OUTPUT 0 1 0 0 Q3
71 - - A -- OUTPUT 0 1 0 0 Q4
58 - - C -- OUTPUT 0 1 0 0 Q5
52 - - - 19 OUTPUT 0 1 0 0 Q6
24 - - B -- OUTPUT 0 1 0 0 Q7
11 - - - 01 OUTPUT 0 1 0 0 USEDW0
64 - - B -- OUTPUT 0 1 0 0 USEDW1
25 - - B -- OUTPUT 0 1 0 0 USEDW2
23 - - B -- OUTPUT 0 1 0 0 USEDW3
35 - - - 06 OUTPUT 0 1 0 0 USEDW4
67 - - B -- OUTPUT 0 1 0 0 USEDW5
66 - - B -- OUTPUT 0 1 0 0 USEDW6
65 - - B -- OUTPUT 0 1 0 0 USEDW7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\maxplus\max2work\tran\testfifo.rpt
testfifo
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 07 DFFE + 1 2 1 5 |CSFIFO:1|a_fefifo:fifo_state|b_full
- 5 - B 07 DFFE + 1 2 1 6 |CSFIFO:1|a_fefifo:fifo_state|b_non_empty
- 2 - B 07 OR2 s 1 2 0 1 |CSFIFO:1|a_fefifo:fifo_state|~113~1
- 3 - B 07 OR2 s 0 4 0 1 |CSFIFO:1|a_fefifo:fifo_state|~113~2
- 4 - B 07 OR2 s 0 4 0 1 |CSFIFO:1|a_fefifo:fifo_state|~113~3
- 2 - B 02 OR2 s ! 0 4 0 2 |CSFIFO:1|a_fefifo:fifo_state|~124~1
- 6 - B 07 AND2 s 1 2 0 1 |CSFIFO:1|a_fefifo:fifo_state|~124~2
- 7 - B 07 AND2 s 0 4 0 1 |CSFIFO:1|a_fefifo:fifo_state|~124~3
- 8 - B 07 AND2 s 0 4 0 1 |CSFIFO:1|a_fefifo:fifo_state|~124~4
- - 6 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_0
- - 3 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_1
- - 2 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_2
- - 5 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_3
- - 8 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_4
- - 7 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_5
- - 1 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_6
- - 4 B -- MEM_SGMT 1 9 0 1 |CSFIFO:1|altram:ram_block|segment0_7
- 1 - B 02 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:77|result_node
- 5 - B 09 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:92|result_node
- 3 - B 10 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:107|result_node
- 1 - B 11 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:122|result_node
- 1 - B 10 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:137|result_node
- 5 - B 01 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:152|result_node
- 6 - B 04 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:167|result_node
- 2 - B 04 OR2 0 3 0 8 |CSFIFO:1|busmux:233|lpm_mux:52|muxlut:182|result_node
- 2 - B 10 DFFE + 0 1 0 1 |CSFIFO:1|clock_reset
- 8 - B 10 DFFE + 0 1 0 11 |CSFIFO:1|clock_shadow
- 1 - B 05 OR2 0 4 0 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry1
- 3 - B 05 OR2 0 3 0 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry2
- 6 - B 05 OR2 0 3 0 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry3
- 8 - B 05 OR2 0 3 0 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry4
- 5 - B 04 OR2 0 3 0 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry5
- 7 - B 04 OR2 0 3 0 1 |CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry6
- 4 - B 02 OR2 0 2 1 0 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:147
- 7 - B 02 OR2 0 4 1 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:156
- 7 - B 05 OR2 0 3 1 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:157
- 4 - B 05 OR2 0 3 1 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:158
- 5 - B 05 OR2 0 3 1 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:159
- 1 - B 01 OR2 0 3 1 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:160
- 3 - B 04 OR2 0 3 1 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:161
- 8 - B 04 OR2 0 3 1 2 |CSFIFO:1|lpm_add_sub:260|addcore:adder|:162
- 3 - B 09 DFFE + 1 1 0 8 |CSFIFO:1|lpm_counter:rd_ptr|dffs0
- 8 - B 09 DFFE + 1 2 0 5 |CSFIFO:1|lpm_counter:rd_ptr|dffs1
- 7 - B 09 DFFE + 0 3 0 4 |CSFIFO:1|lpm_counter:rd_ptr|dffs2
- 2 - B 11 DFFE + 0 2 0 6 |CSFIFO:1|lpm_counter:rd_ptr|dffs3
- 4 - B 11 DFFE + 0 3 0 5 |CSFIFO:1|lpm_counter:rd_ptr|dffs4
- 7 - B 11 DFFE + 0 3 0 4 |CSFIFO:1|lpm_counter:rd_ptr|dffs5
- 3 - B 11 DFFE + 0 2 0 4 |CSFIFO:1|lpm_counter:rd_ptr|dffs6
- 6 - B 11 DFFE + 0 3 0 2 |CSFIFO:1|lpm_counter:rd_ptr|dffs7
- 4 - B 09 AND2 0 3 0 4 |CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:125
- 5 - B 11 AND2 0 2 0 1 |CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:129
- 8 - B 11 AND2 0 4 0 2 |CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:137
- 5 - B 02 DFFE + 1 1 0 8 |CSFIFO:1|lpm_counter:wr_ptr|dffs0
- 8 - B 02 DFFE + 0 2 0 5 |CSFIFO:1|lpm_counter:wr_ptr|dffs1
- 2 - B 05 DFFE + 0 3 0 4 |CSFIFO:1|lpm_counter:wr_ptr|dffs2
- 4 - B 01 DFFE + 0 2 0 6 |CSFIFO:1|lpm_counter:wr_ptr|dffs3
- 2 - B 01 DFFE + 0 3 0 5 |CSFIFO:1|lpm_counter:wr_ptr|dffs4
- 3 - B 01 DFFE + 0 3 0 4 |CSFIFO:1|lpm_counter:wr_ptr|dffs5
- 1 - B 04 DFFE + 0 2 0 4 |CSFIFO:1|lpm_counter:wr_ptr|dffs6
- 4 - B 04 DFFE + 0 3 0 2 |CSFIFO:1|lpm_counter:wr_ptr|dffs7
- 6 - B 01 AND2 0 3 0 4 |CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:125
- 7 - B 01 AND2 0 2 0 1 |CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:129
- 8 - B 01 AND2 0 4 0 2 |CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:137
- 7 - B 20 DFFE + 0 2 1 0 |CSFIFO:1|rd_out0
- 1 - B 20 DFFE + 0 2 1 0 |CSFIFO:1|rd_out1
- 6 - B 09 DFFE + 0 2 1 0 |CSFIFO:1|rd_out2
- 2 - B 20 DFFE + 0 2 1 0 |CSFIFO:1|rd_out3
- 3 - B 20 DFFE + 0 2 1 0 |CSFIFO:1|rd_out4
- 6 - B 20 DFFE + 0 2 1 0 |CSFIFO:1|rd_out5
- 4 - B 20 DFFE + 0 2 1 0 |CSFIFO:1|rd_out6
- 5 - B 20 DFFE + 0 2 1 0 |CSFIFO:1|rd_out7
- 2 - B 09 OR2 ! 1 1 0 6 |CSFIFO:1|valid_rreq
- 6 - B 02 OR2 ! 1 1 0 7 |CSFIFO:1|valid_wreq
- 3 - B 02 AND2 1 2 0 8 |CSFIFO:1|:312
- 1 - B 09 AND2 1 2 0 8 |CSFIFO:1|:314
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus\max2work\tran\testfifo.rpt
testfifo
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 32/ 96( 33%) 31/ 48( 64%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus\max2work\tran\testfifo.rpt
testfifo
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 36 CLK
Device-Specific Information: d:\maxplus\max2work\tran\testfifo.rpt
testfifo
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 26 CLR
DFF 11 |CSFIFO:1|clock_shadow
DFF 1 |CSFIFO:1|clock_reset
Device-Specific Information: d:\maxplus\max2work\tran\testfifo.rpt
testfifo
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
INDATA0 : INPUT;
INDATA1 : INPUT;
INDATA2 : INPUT;
INDATA3 : INPUT;
INDATA4 : INPUT;
INDATA5 : INPUT;
INDATA6 : INPUT;
INDATA7 : INPUT;
RD : INPUT;
WR : INPUT;
-- Node name is 'EMPTY'
-- Equation name is 'EMPTY', type is output
EMPTY = !_LC5_B7;
-- Node name is 'FULL'
-- Equation name is 'FULL', type is output
FULL = _LC1_B7;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC7_B20;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC1_B20;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC6_B9;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC2_B20;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = _LC3_B20;
-- Node name is 'Q5'
-- Equation name is 'Q5', type is output
Q5 = _LC6_B20;
-- Node name is 'Q6'
-- Equation name is 'Q6', type is output
Q6 = _LC4_B20;
-- Node name is 'Q7'
-- Equation name is 'Q7', type is output
Q7 = _LC5_B20;
-- Node name is 'USEDW0'
-- Equation name is 'USEDW0', type is output
USEDW0 = !_LC4_B2;
-- Node name is 'USEDW1'
-- Equation name is 'USEDW1', type is output
USEDW1 = _LC7_B2;
-- Node name is 'USEDW2'
-- Equation name is 'USEDW2', type is output
USEDW2 = _LC7_B5;
-- Node name is 'USEDW3'
-- Equation name is 'USEDW3', type is output
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