📄 fec_inter_mux.rpt
字号:
B6 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 4/22( 18%)
B8 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
B9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 3/22( 13%)
C1 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 5/22( 22%)
C2 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 1/2 5/22( 22%)
C5 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 5/22( 22%)
C7 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 2/2 1/2 5/22( 22%)
C9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 1/22( 4%)
E1 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
E2 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 10/22( 45%)
E3 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
E4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
E5 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
E6 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
E7 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
E8 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 10/22( 45%)
E9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
E12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
E13 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
E14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
E15 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 3/22( 13%)
E16 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 9/22( 40%)
E17 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 9/22( 40%)
E19 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 9/22( 40%)
E20 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
E21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
E22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
E23 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 3/22( 13%)
F1 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
F2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
F3 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
F4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 10/22( 45%)
F5 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
F6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
F7 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 14/22( 63%)
F8 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 15/22( 68%)
F9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
F10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 10/22( 45%)
F11 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
F12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 5/22( 22%)
F13 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 11/22( 50%)
F14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
F15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 4/22( 18%)
F16 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 11/22( 50%)
F17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 8/22( 36%)
F18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
F19 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 11/22( 50%)
F20 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 1/2 8/22( 36%)
F21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
F22 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 2/2 1/2 1/22( 4%)
F23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
F24 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 5/22( 22%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 22/96 ( 22%)
Total logic cells used: 544/1152 ( 47%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 1.83/4 ( 45%)
Total fan-in: 1000/4608 ( 21%)
Total input pins required: 16
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 544
Total flipflops required: 384
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 36/1152 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 2 8 8 8 8 8 8 8 1 8 0 7 6 6 8 0 8 0 1 7 8 0 8 142/0
B: 0 0 8 0 8 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40/0
C: 8 8 0 0 8 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 3 8 8 8 7 8 8 8 8 0 0 8 0 3 8 7 8 8 0 8 8 8 8 4 0 144/0
F: 6 8 6 8 6 8 8 8 8 8 7 8 0 8 8 8 8 8 8 8 8 8 2 8 7 178/0
Total: 25 32 24 24 37 32 32 32 40 16 8 24 0 18 22 21 24 16 16 16 17 23 18 12 15 544/0
Device-Specific Information: e:\work\20\tran\fec_inter_mux.rpt
fec_inter_mux
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
56 - - - -- INPUT 0 0 0 96 AD0
124 - - - -- INPUT 0 0 0 88 AD1
126 - - - -- INPUT 0 0 0 48 AD2
80 - - F -- INPUT 0 0 0 16 AD3
32 - - F -- INPUT 0 0 0 8 AD4
54 - - - -- INPUT G 0 0 0 0 /CLR_L
64 - - - 09 INPUT 0 0 0 3 D0
67 - - - 08 INPUT 0 0 0 3 D1
73 - - - 01 INPUT 0 0 0 3 D2
63 - - - 10 INPUT 0 0 0 3 D3
111 - - - 01 INPUT 0 0 0 4 D4
116 - - - 04 INPUT 0 0 0 4 D5
113 - - - 03 INPUT 0 0 0 4 D6
120 - - - 08 INPUT 0 0 0 4 D7
125 - - - -- INPUT G 0 0 0 0 LOCKCLK
55 - - - -- INPUT G 0 0 0 0 OUTCLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\work\20\tran\fec_inter_mux.rpt
fec_inter_mux
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - E -- OUTPUT 0 1 0 0 FD0
87 - - E -- OUTPUT 0 1 0 0 FD1
27 - - E -- OUTPUT 0 1 0 0 FD2
99 - - B -- OUTPUT 0 1 0 0 FD3
102 - - A -- OUTPUT 0 1 0 0 RESULT0
100 - - A -- OUTPUT 0 1 0 0 RESULT1
144 - - A -- OUTPUT 0 1 0 0 RESULT2
7 - - A -- OUTPUT 0 1 0 0 RESULT3
81 - - F -- OUTPUT 0 1 0 0 RESULT4
8 - - A -- OUTPUT 0 1 0 0 RESULT5
79 - - F -- OUTPUT 0 1 0 0 RESULT6
143 - - A -- OUTPUT 0 1 0 0 RESULT7
Code:
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