📄 fec_inter_mux.rpt
字号:
|lpm_mux:60|muxlut:492|muxlut:96|
|lpm_mux:60|muxlut:492|muxlut:96|muxlut:45|
|lpm_mux:60|muxlut:492|muxlut:96|muxlut:64|
|lpm_mux:60|muxlut:492|muxlut:96|muxlut:83|
|lpm_mux:60|muxlut:492|muxlut:120|
|lpm_mux:60|muxlut:533|
|lpm_mux:60|muxlut:533|muxlut:63|
|lpm_mux:60|muxlut:533|muxlut:63|muxlut:54|
|lpm_mux:60|muxlut:533|muxlut:63|muxlut:73|
|lpm_mux:60|muxlut:533|muxlut:63|muxlut:92|
|lpm_mux:60|muxlut:533|muxlut:63|muxlut:111|
|lpm_mux:60|muxlut:533|muxlut:63|muxlut:130|
|lpm_mux:60|muxlut:533|muxlut:96|
|lpm_mux:60|muxlut:533|muxlut:96|muxlut:45|
|lpm_mux:60|muxlut:533|muxlut:96|muxlut:64|
|lpm_mux:60|muxlut:533|muxlut:96|muxlut:83|
|lpm_mux:60|muxlut:533|muxlut:120|
|lpm_mux:60|muxlut:574|
|lpm_mux:60|muxlut:574|muxlut:63|
|lpm_mux:60|muxlut:574|muxlut:63|muxlut:54|
|lpm_mux:60|muxlut:574|muxlut:63|muxlut:73|
|lpm_mux:60|muxlut:574|muxlut:63|muxlut:92|
|lpm_mux:60|muxlut:574|muxlut:63|muxlut:111|
|lpm_mux:60|muxlut:574|muxlut:63|muxlut:130|
|lpm_mux:60|muxlut:574|muxlut:96|
|lpm_mux:60|muxlut:574|muxlut:96|muxlut:45|
|lpm_mux:60|muxlut:574|muxlut:96|muxlut:64|
|lpm_mux:60|muxlut:574|muxlut:96|muxlut:83|
|lpm_mux:60|muxlut:574|muxlut:120|
Device-Specific Information: e:\work\20\tran\fec_inter_mux.rpt
fec_inter_mux
***** Logic for device 'fec_inter_mux' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R
R R E E E E E E E E E E E E L E E E E E E E E E
E E S S S S S S S S S S S S G O V S S S S S S S S S
S S E E E G E E E E V E E E E G E N C C E E E E E V E E E E
U U R R R N R R R R C R R R R N R D K C R R R R R C R R R R
L L V V V D V V V V C V V V V D V I A C A I V V V V V C V V V V
T T E E E I E E E E I E E E E I E N D L D N E E D E E E D I E D E D E E
2 7 D D D O D D D D O D D D D O D T 2 K 1 T D D 7 D D D 5 O D 6 D 4 D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESULT3 | 7 102 | RESULT0
RESULT5 | 8 101 | RESERVED
RESERVED | 9 100 | RESULT1
RESERVED | 10 99 | FD3
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K20TC144-3 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | FD1
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | FD0
FD2 | 27 82 | RESERVED
RESERVED | 28 81 | RESULT4
RESERVED | 29 80 | AD3
RESERVED | 30 79 | RESULT6
RESERVED | 31 78 | RESERVED
AD4 | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | D2
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R G R V V / O A G G R R V R D D R G D R R R V R
E E E N E E E E C E E E E N E C C C U D N N E E C E 3 0 E N 1 E E E C E
S S S D S S S S C S S S S D S C C L T 0 D D S S C S S D S S S C S
E E E I E E E E I E E E E I E I I R C I I E E I E E I E E E I E
R R R O R R R R O R R R R O R N N _ L N N R R O R R O R R R O R
V V V V V V V V V V V V T T L K T T V V V V V V V V
E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\work\20\tran\fec_inter_mux.rpt
fec_inter_mux
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 11/22( 50%)
A2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
A3 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 1/22( 4%)
A4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
A5 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 9/22( 40%)
A6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 7/22( 31%)
A7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 8/22( 36%)
A8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 4/22( 18%)
A9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 1/22( 4%)
A10 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 1/2 11/22( 50%)
A11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 8/22( 36%)
A13 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
A14 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 1/22( 4%)
A15 6/ 8( 75%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 19/22( 86%)
A16 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
A18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 4/22( 18%)
A20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A21 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 4/22( 18%)
A22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
A24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 1/2 11/22( 50%)
B3 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 4/22( 18%)
B5 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 1/2 4/22( 18%)
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