tran.rpt

在Maxplus软件平台开发的

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Device-Specific Information:                     e:\work\maxplus\tran\tran.rpt
tran

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        5         /WR
INPUT        1         CLK


Device-Specific Information:                     e:\work\maxplus\tran\tran.rpt
tran

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        6         /CLR


Device-Specific Information:                     e:\work\maxplus\tran\tran.rpt
tran

** EQUATIONS **

CLK      : INPUT;
D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;
D4       : INPUT;
D5       : INPUT;
D6       : INPUT;
D7       : INPUT;
/CLR     : INPUT;
/WR      : INPUT;

-- Node name is 'C' 
-- Equation name is 'C', type is output 
C        =  _LC4_F11;

-- Node name is 'FD0' 
-- Equation name is 'FD0', type is output 
FD0      =  _LC2_E23;

-- Node name is 'FD1' 
-- Equation name is 'FD1', type is output 
FD1      =  _LC8_E23;

-- Node name is 'FD2' 
-- Equation name is 'FD2', type is output 
FD2      =  _LC3_E23;

-- Node name is 'FD3' 
-- Equation name is 'FD3', type is output 
FD3      =  _LC4_E23;

-- Node name is '|fec:2|fec-1:18|8and:22|:38' = '|fec:2|fec-1:18|8and:22|OUT' 
-- Equation name is '_LC8_E23', type is buried 
_LC8_E23 = LCELL( _EQ001);
  _EQ001 =  D5 &  D7 &  _LC5_E23
         # !D5 &  D7 & !_LC5_E23
         # !D5 & !D7 &  _LC5_E23
         #  D5 & !D7 & !_LC5_E23;

-- Node name is '|fec:2|fec-1:18|8and:22|~38~1' = '|fec:2|fec-1:18|8and:22|OUT~1' 
-- Equation name is '_LC5_E23', type is buried 
-- synthesized logic cell 
_LC5_E23 = LCELL( _EQ002);
  _EQ002 = !D1 &  D3 & !D4
         #  D1 & !D3 & !D4
         #  D1 &  D3 &  D4
         # !D1 & !D3 &  D4;

-- Node name is '|fec:2|fec-1:18|8and:23|:38' = '|fec:2|fec-1:18|8and:23|OUT' 
-- Equation name is '_LC2_E23', type is buried 
_LC2_E23 = LCELL( _EQ003);
  _EQ003 =  D5 &  D6 &  _LC1_E23
         #  D5 & !D6 & !_LC1_E23
         # !D5 &  D6 & !_LC1_E23
         # !D5 & !D6 &  _LC1_E23;

-- Node name is '|fec:2|fec-1:18|8and:23|~38~1' = '|fec:2|fec-1:18|8and:23|OUT~1' 
-- Equation name is '_LC1_E23', type is buried 
-- synthesized logic cell 
_LC1_E23 = LCELL( _EQ004);
  _EQ004 =  D0 &  D2 &  D4
         # !D0 & !D2 &  D4
         # !D0 &  D2 & !D4
         #  D0 & !D2 & !D4;

-- Node name is '|fec:2|fec-1:18|8and:24|:38' = '|fec:2|fec-1:18|8and:24|OUT' 
-- Equation name is '_LC3_E23', type is buried 
_LC3_E23 = LCELL( _EQ005);
  _EQ005 = !D6 & !D7 &  _LC6_E23
         #  D6 & !D7 & !_LC6_E23
         #  D6 &  D7 &  _LC6_E23
         # !D6 &  D7 & !_LC6_E23;

-- Node name is '|fec:2|fec-1:18|8and:24|~38~1' = '|fec:2|fec-1:18|8and:24|OUT~1' 
-- Equation name is '_LC6_E23', type is buried 
-- synthesized logic cell 
_LC6_E23 = LCELL( _EQ006);
  _EQ006 = !D0 &  D1 & !D4
         #  D0 & !D1 & !D4
         #  D0 &  D1 &  D4
         # !D0 & !D1 &  D4;

-- Node name is '|fec:2|fec-1:18|8and:25|:38' = '|fec:2|fec-1:18|8and:25|OUT' 
-- Equation name is '_LC4_E23', type is buried 
_LC4_E23 = LCELL( _EQ007);
  _EQ007 = !D5 & !D7 &  _LC7_E23
         #  D5 & !D7 & !_LC7_E23
         #  D5 &  D7 &  _LC7_E23
         # !D5 &  D7 & !_LC7_E23;

-- Node name is '|fec:2|fec-1:18|8and:25|~38~1' = '|fec:2|fec-1:18|8and:25|OUT~1' 
-- Equation name is '_LC7_E23', type is buried 
-- synthesized logic cell 
_LC7_E23 = LCELL( _EQ008);
  _EQ008 = !D2 &  D3 & !D6
         #  D2 & !D3 & !D6
         #  D2 &  D3 &  D6
         # !D2 & !D3 &  D6;

-- Node name is '|74161ca2:183|:13' = '|74161ca2:183|c_clk' 
-- Equation name is '_LC4_F11', type is buried 
_LC4_F11 = DFFE( _LC6_F11, GLOBAL(!CLK), GLOBAL( /CLR),  VCC,  VCC);

-- Node name is '|74161ca2:183|74161ca:1|:1' = '|74161ca2:183|74161ca:1|C' 
-- Equation name is '_LC6_F11', type is buried 
_LC6_F11 = DFFE( _EQ009,  /WR, GLOBAL( /CLR),  VCC,  VCC);
  _EQ009 =  _LC1_F11 &  _LC2_F11 &  _LC3_F11 &  _LC5_F11;

-- Node name is '|74161ca2:183|74161ca:1|74161:9|f74161:sub|:9' = '|74161ca2:183|74161ca:1|74161:9|f74161:sub|QA' 
-- Equation name is '_LC2_F11', type is buried 
_LC2_F11 = DFFE(!_LC2_F11,  /WR, GLOBAL( /CLR),  VCC,  VCC);

-- Node name is '|74161ca2:183|74161ca:1|74161:9|f74161:sub|:87' = '|74161ca2:183|74161ca:1|74161:9|f74161:sub|QB' 
-- Equation name is '_LC1_F11', type is buried 
_LC1_F11 = DFFE( _EQ010,  /WR, GLOBAL( /CLR),  VCC,  VCC);
  _EQ010 = !_LC1_F11 &  _LC2_F11
         #  _LC1_F11 & !_LC2_F11;

-- Node name is '|74161ca2:183|74161ca:1|74161:9|f74161:sub|:99' = '|74161ca2:183|74161ca:1|74161:9|f74161:sub|QC' 
-- Equation name is '_LC3_F11', type is buried 
_LC3_F11 = DFFE( _EQ011,  /WR, GLOBAL( /CLR),  VCC,  VCC);
  _EQ011 = !_LC2_F11 &  _LC3_F11
         # !_LC1_F11 &  _LC3_F11
         #  _LC1_F11 &  _LC2_F11 & !_LC3_F11;

-- Node name is '|74161ca2:183|74161ca:1|74161:9|f74161:sub|:110' = '|74161ca2:183|74161ca:1|74161:9|f74161:sub|QD' 
-- Equation name is '_LC5_F11', type is buried 
_LC5_F11 = DFFE( _EQ012,  /WR, GLOBAL( /CLR),  VCC,  VCC);
  _EQ012 = !_LC2_F11 &  _LC5_F11
         # !_LC1_F11 &  _LC5_F11
         # !_LC3_F11 &  _LC5_F11
         #  _LC1_F11 &  _LC2_F11 &  _LC3_F11 & !_LC5_F11;



Project Information                              e:\work\maxplus\tran\tran.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 21,542K