📄 tri8.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\work\20\tran\tri8.rpt
tri8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - E 01 LCELL s 1 0 1 0 ~18~1
- 3 - F 17 LCELL s 1 0 1 0 ~19~1
- 1 - A 05 LCELL s 1 0 1 0 ~20~1
- 2 - F 09 LCELL s 1 0 1 0 ~21~1
- 8 - A 18 LCELL s 1 0 1 0 ~22~1
- 5 - F 18 LCELL s 1 0 1 0 ~23~1
- 4 - C 11 LCELL s 1 0 1 0 ~24~1
- 5 - B 21 LCELL s 1 0 1 0 ~25~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\work\20\tran\tri8.rpt
tri8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 1/ 48( 2%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
F: 2/ 96( 2%) 0/ 48( 0%) 2/ 48( 4%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\work\20\tran\tri8.rpt
tri8
** EQUATIONS **
en : INPUT;
in0 : INPUT;
in1 : INPUT;
in2 : INPUT;
in3 : INPUT;
in4 : INPUT;
in5 : INPUT;
in6 : INPUT;
in7 : INPUT;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = TRI(_LC5_B21, GLOBAL( en));
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = TRI(_LC4_C11, GLOBAL( en));
-- Node name is 'out2'
-- Equation name is 'out2', type is output
out2 = TRI(_LC5_F18, GLOBAL( en));
-- Node name is 'out3'
-- Equation name is 'out3', type is output
out3 = TRI(_LC8_A18, GLOBAL( en));
-- Node name is 'out4'
-- Equation name is 'out4', type is output
out4 = TRI(_LC2_F9, GLOBAL( en));
-- Node name is 'out5'
-- Equation name is 'out5', type is output
out5 = TRI(_LC1_A5, GLOBAL( en));
-- Node name is 'out6'
-- Equation name is 'out6', type is output
out6 = TRI(_LC3_F17, GLOBAL( en));
-- Node name is 'out7'
-- Equation name is 'out7', type is output
out7 = TRI(_LC6_E1, GLOBAL( en));
-- Node name is '~18~1'
-- Equation name is '~18~1', location is LC6_E1, type is buried.
-- synthesized logic cell
_LC6_E1 = LCELL( in7);
-- Node name is '~19~1'
-- Equation name is '~19~1', location is LC3_F17, type is buried.
-- synthesized logic cell
_LC3_F17 = LCELL( in6);
-- Node name is '~20~1'
-- Equation name is '~20~1', location is LC1_A5, type is buried.
-- synthesized logic cell
_LC1_A5 = LCELL( in5);
-- Node name is '~21~1'
-- Equation name is '~21~1', location is LC2_F9, type is buried.
-- synthesized logic cell
_LC2_F9 = LCELL( in4);
-- Node name is '~22~1'
-- Equation name is '~22~1', location is LC8_A18, type is buried.
-- synthesized logic cell
_LC8_A18 = LCELL( in3);
-- Node name is '~23~1'
-- Equation name is '~23~1', location is LC5_F18, type is buried.
-- synthesized logic cell
_LC5_F18 = LCELL( in2);
-- Node name is '~24~1'
-- Equation name is '~24~1', location is LC4_C11, type is buried.
-- synthesized logic cell
_LC4_C11 = LCELL( in1);
-- Node name is '~25~1'
-- Equation name is '~25~1', location is LC5_B21, type is buried.
-- synthesized logic cell
_LC5_B21 = LCELL( in0);
Project Information e:\work\20\tran\tri8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,166K
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