testfifo.fit

在Maxplus软件平台开发的

-- MAX+plus II Compiler Fit File      
-- Version 10.0 9/14/2000             
-- Compiled: 02/17/2003 19:44:20      

-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "testfifo"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "CLK"                          : INPUT_PIN  = 1      ;
    "CLR"                          : INPUT_PIN  = 2      ;
    "INDATA0"                      : INPUT_PIN  = 84     ;
    "INDATA1"                      : INPUT_PIN  = 43     ;
    "INDATA2"                      : INPUT_PIN  = 10     ;
    "INDATA3"                      : INPUT_PIN  = 37     ;
    "INDATA4"                      : INPUT_PIN  = 39     ;
    "INDATA5"                      : INPUT_PIN  = 6      ;
    "INDATA6"                      : INPUT_PIN  = 7      ;
    "INDATA7"                      : INPUT_PIN  = 5      ;
    "RD"                           : INPUT_PIN  = 44     ;
    "WR"                           : INPUT_PIN  = 42     ;
    "EMPTY"                        : OUTPUT_PIN = 70     ;
    "FULL"                         : OUTPUT_PIN = 21     ;
    "Q0"                           : OUTPUT_PIN = 53     ;
    "Q1"                           : OUTPUT_PIN = 22     ;
    "Q2"                           : OUTPUT_PIN = 38     ;
    "Q3"                           : OUTPUT_PIN = 72     ;
    "Q4"                           : OUTPUT_PIN = 71     ;
    "Q5"                           : OUTPUT_PIN = 58     ;
    "Q6"                           : OUTPUT_PIN = 52     ;
    "Q7"                           : OUTPUT_PIN = 24     ;
    "USEDW0"                       : OUTPUT_PIN = 11     ;
    "USEDW1"                       : OUTPUT_PIN = 64     ;
    "USEDW2"                       : OUTPUT_PIN = 25     ;
    "USEDW3"                       : OUTPUT_PIN = 23     ;
    "USEDW4"                       : OUTPUT_PIN = 35     ;
    "USEDW5"                       : OUTPUT_PIN = 67     ;
    "USEDW6"                       : OUTPUT_PIN = 66     ;
    "USEDW7"                       : OUTPUT_PIN = 65     ;
    "|CSFIFO:1|a_fefifo:fifo_state|b_full" : LOCATION   = LC1_B7 ;
    "|CSFIFO:1|a_fefifo:fifo_state|b_non_empty" : LOCATION   = LC5_B7 ;
    "|CSFIFO:1|a_fefifo:fifo_state|~113~1" : LOCATION   = LC2_B7 ;
    "|CSFIFO:1|a_fefifo:fifo_state|~113~2" : LOCATION   = LC3_B7 ;
    "|CSFIFO:1|a_fefifo:fifo_state|~113~3" : LOCATION   = LC4_B7 ;
    "|CSFIFO:1|a_fefifo:fifo_state|~124~1" : LOCATION   = LC2_B2 ;
    "|CSFIFO:1|a_fefifo:fifo_state|~124~2" : LOCATION   = LC6_B7 ;
    "|CSFIFO:1|a_fefifo:fifo_state|~124~3" : LOCATION   = LC7_B7 ;
    "|CSFIFO:1|a_fefifo:fifo_state|~124~4" : LOCATION   = LC8_B7 ;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:77|result_node" : LOCATION   = LC1_B2 ;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:92|result_node" : LOCATION   = LC5_B9 ;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:107|result_node" : LOCATION   = LC3_B10;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:122|result_node" : LOCATION   = LC1_B11;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:137|result_node" : LOCATION   = LC1_B10;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:152|result_node" : LOCATION   = LC5_B1 ;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:167|result_node" : LOCATION   = LC6_B4 ;
    "|CSFIFO:1|busmux:233|lpm_mux:52|muxlut:182|result_node" : LOCATION   = LC2_B4 ;
    "|CSFIFO:1|clock_reset"        : LOCATION   = LC2_B10;
    "|CSFIFO:1|clock_shadow"       : LOCATION   = LC8_B10;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry1" : LOCATION   = LC1_B5 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry2" : LOCATION   = LC3_B5 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry3" : LOCATION   = LC6_B5 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry4" : LOCATION   = LC8_B5 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry5" : LOCATION   = LC5_B4 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|pcarry6" : LOCATION   = LC7_B4 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:147" : LOCATION   = LC4_B2 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:156" : LOCATION   = LC7_B2 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:157" : LOCATION   = LC7_B5 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:158" : LOCATION   = LC4_B5 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:159" : LOCATION   = LC5_B5 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:160" : LOCATION   = LC1_B1 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:161" : LOCATION   = LC3_B4 ;
    "|CSFIFO:1|lpm_add_sub:260|addcore:adder|:162" : LOCATION   = LC8_B4 ;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs0" : LOCATION   = LC3_B9 ;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs1" : LOCATION   = LC8_B9 ;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs2" : LOCATION   = LC7_B9 ;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs3" : LOCATION   = LC2_B11;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs4" : LOCATION   = LC4_B11;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs5" : LOCATION   = LC7_B11;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs6" : LOCATION   = LC3_B11;
    "|CSFIFO:1|lpm_counter:rd_ptr|dffs7" : LOCATION   = LC6_B11;
    "|CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:125" : LOCATION   = LC4_B9 ;
    "|CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:129" : LOCATION   = LC5_B11;
    "|CSFIFO:1|lpm_counter:rd_ptr|lpm_add_sub:add_sub|addcore:adder|:137" : LOCATION   = LC8_B11;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs0" : LOCATION   = LC5_B2 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs1" : LOCATION   = LC8_B2 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs2" : LOCATION   = LC2_B5 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs3" : LOCATION   = LC4_B1 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs4" : LOCATION   = LC2_B1 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs5" : LOCATION   = LC3_B1 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs6" : LOCATION   = LC1_B4 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|dffs7" : LOCATION   = LC4_B4 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:125" : LOCATION   = LC6_B1 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:129" : LOCATION   = LC7_B1 ;
    "|CSFIFO:1|lpm_counter:wr_ptr|lpm_add_sub:add_sub|addcore:adder|:137" : LOCATION   = LC8_B1 ;
    "|CSFIFO:1|rd_out0"            : LOCATION   = LC7_B20;
    "|CSFIFO:1|rd_out1"            : LOCATION   = LC1_B20;
    "|CSFIFO:1|rd_out2"            : LOCATION   = LC6_B9 ;
    "|CSFIFO:1|rd_out3"            : LOCATION   = LC2_B20;
    "|CSFIFO:1|rd_out4"            : LOCATION   = LC3_B20;
    "|CSFIFO:1|rd_out5"            : LOCATION   = LC6_B20;
    "|CSFIFO:1|rd_out6"            : LOCATION   = LC4_B20;
    "|CSFIFO:1|rd_out7"            : LOCATION   = LC5_B20;
    "|CSFIFO:1|valid_rreq"         : LOCATION   = LC2_B9 ;
    "|CSFIFO:1|valid_wreq"         : LOCATION   = LC6_B2 ;
    "|CSFIFO:1|:312"               : LOCATION   = LC3_B2 ;
    "|CSFIFO:1|:314"               : LOCATION   = LC1_B9 ;
    "|CSFIFO:1|altram:ram_block|segment0_0" : LOCATION   = EC6_B  ;
    "|CSFIFO:1|altram:ram_block|segment0_1" : LOCATION   = EC3_B  ;
    "|CSFIFO:1|altram:ram_block|segment0_2" : LOCATION   = EC2_B  ;
    "|CSFIFO:1|altram:ram_block|segment0_3" : LOCATION   = EC5_B  ;
    "|CSFIFO:1|altram:ram_block|segment0_4" : LOCATION   = EC8_B  ;
    "|CSFIFO:1|altram:ram_block|segment0_5" : LOCATION   = EC7_B  ;
    "|CSFIFO:1|altram:ram_block|segment0_6" : LOCATION   = EC1_B  ;
    "|CSFIFO:1|altram:ram_block|segment0_7" : LOCATION   = EC4_B  ;

END;

INTERNAL_INFO "testfifo"