📄 seladdress.rpt
字号:
91 - - C -- OUTPUT 0 1 0 0 /CS_TRAN
12 - - C -- OUTPUT 0 1 0 0 /CS_8251
92 - - C -- OUTPUT 0 1 0 0 /RESET
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\work\20\tran\seladdress.rpt
seladdress
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 20 OR2 2 0 1 0 :8
- 4 - C 20 OR2 3 0 1 0 |74138:6|Y1N (|74138:6|:16)
- 5 - C 20 OR2 3 0 1 0 |74138:6|Y2N (|74138:6|:17)
- 1 - C 20 OR2 3 0 1 0 |74138:6|Y3N (|74138:6|:18)
- 3 - C 20 AND2 ! 3 0 1 0 |74138:6|Y4N (|74138:6|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\work\20\tran\seladdress.rpt
seladdress
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\work\20\tran\seladdress.rpt
seladdress
** EQUATIONS **
d13 : INPUT;
d14 : INPUT;
d15 : INPUT;
-- Node name is 'C/D'
-- Equation name is 'C/D', type is output
C/D = !_LC3_C20;
-- Node name is '|74138:6|:16' = '|74138:6|Y1N'
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = LCELL( _EQ001);
_EQ001 = d14
# d15
# !d13;
-- Node name is '|74138:6|:17' = '|74138:6|Y2N'
-- Equation name is '_LC5_C20', type is buried
_LC5_C20 = LCELL( _EQ002);
_EQ002 = !d14
# d15
# d13;
-- Node name is '|74138:6|:18' = '|74138:6|Y3N'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = LCELL( _EQ003);
_EQ003 = !d14
# d15
# !d13;
-- Node name is '|74138:6|:19' = '|74138:6|Y4N'
-- Equation name is '_LC3_C20', type is buried
!_LC3_C20 = _LC3_C20~NOT;
_LC3_C20~NOT = LCELL( _EQ004);
_EQ004 = !d13 & !d14 & d15;
-- Node name is '/CS_RECV'
-- Equation name is '/CS_RECV', type is output
/CS_RECV = _LC1_C20;
-- Node name is '/CS_TRAN'
-- Equation name is '/CS_TRAN', type is output
/CS_TRAN = _LC5_C20;
-- Node name is '/CS_8251'
-- Equation name is '/CS_8251', type is output
/CS_8251 = _LC2_C20;
-- Node name is '/RESET'
-- Equation name is '/RESET', type is output
/RESET = _LC4_C20;
-- Node name is ':8'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = LCELL( _EQ005);
_EQ005 = d14
# !d15;
Project Information e:\work\20\tran\seladdress.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,379K
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