📄 fec.rpt
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Device-Specific Information: d:\maxplus\max2work\tran\fec.rpt
fec
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - F 22 OR2 s 3 0 0 1 |fec-1:18|8and:22|OUT~1 (|fec-1:18|8and:22|~38~1)
- 5 - F 22 OR2 2 1 1 0 |fec-1:18|8and:22|OUT (|fec-1:18|8and:22|:38)
- 3 - F 22 OR2 s 3 0 0 1 |fec-1:18|8and:23|OUT~1 (|fec-1:18|8and:23|~38~1)
- 2 - F 22 OR2 2 1 1 0 |fec-1:18|8and:23|OUT (|fec-1:18|8and:23|:38)
- 7 - F 22 OR2 s 3 0 0 1 |fec-1:18|8and:24|OUT~1 (|fec-1:18|8and:24|~38~1)
- 1 - F 22 OR2 2 1 1 0 |fec-1:18|8and:24|OUT (|fec-1:18|8and:24|:38)
- 8 - F 22 OR2 s 3 0 0 1 |fec-1:18|8and:25|OUT~1 (|fec-1:18|8and:25|~38~1)
- 4 - F 22 OR2 2 1 1 0 |fec-1:18|8and:25|OUT (|fec-1:18|8and:25|:38)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus\max2work\tran\fec.rpt
fec
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 4/ 96( 4%) 0/ 48( 0%) 2/ 48( 4%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus\max2work\tran\fec.rpt
fec
** EQUATIONS **
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
-- Node name is 'FD0'
-- Equation name is 'FD0', type is output
FD0 = _LC2_F22;
-- Node name is 'FD1'
-- Equation name is 'FD1', type is output
FD1 = _LC5_F22;
-- Node name is 'FD2'
-- Equation name is 'FD2', type is output
FD2 = _LC1_F22;
-- Node name is 'FD3'
-- Equation name is 'FD3', type is output
FD3 = _LC4_F22;
-- Node name is '|fec-1:18|8and:22|:38' = '|fec-1:18|8and:22|OUT'
-- Equation name is '_LC5_F22', type is buried
_LC5_F22 = LCELL( _EQ001);
_EQ001 = D5 & D7 & _LC6_F22
# !D5 & D7 & !_LC6_F22
# !D5 & !D7 & _LC6_F22
# D5 & !D7 & !_LC6_F22;
-- Node name is '|fec-1:18|8and:22|~38~1' = '|fec-1:18|8and:22|OUT~1'
-- Equation name is '_LC6_F22', type is buried
-- synthesized logic cell
_LC6_F22 = LCELL( _EQ002);
_EQ002 = !D1 & D3 & !D4
# D1 & !D3 & !D4
# D1 & D3 & D4
# !D1 & !D3 & D4;
-- Node name is '|fec-1:18|8and:23|:38' = '|fec-1:18|8and:23|OUT'
-- Equation name is '_LC2_F22', type is buried
_LC2_F22 = LCELL( _EQ003);
_EQ003 = D5 & D6 & _LC3_F22
# D5 & !D6 & !_LC3_F22
# !D5 & D6 & !_LC3_F22
# !D5 & !D6 & _LC3_F22;
-- Node name is '|fec-1:18|8and:23|~38~1' = '|fec-1:18|8and:23|OUT~1'
-- Equation name is '_LC3_F22', type is buried
-- synthesized logic cell
_LC3_F22 = LCELL( _EQ004);
_EQ004 = D0 & D2 & D4
# !D0 & !D2 & D4
# !D0 & D2 & !D4
# D0 & !D2 & !D4;
-- Node name is '|fec-1:18|8and:24|:38' = '|fec-1:18|8and:24|OUT'
-- Equation name is '_LC1_F22', type is buried
_LC1_F22 = LCELL( _EQ005);
_EQ005 = !D6 & !D7 & _LC7_F22
# D6 & !D7 & !_LC7_F22
# D6 & D7 & _LC7_F22
# !D6 & D7 & !_LC7_F22;
-- Node name is '|fec-1:18|8and:24|~38~1' = '|fec-1:18|8and:24|OUT~1'
-- Equation name is '_LC7_F22', type is buried
-- synthesized logic cell
_LC7_F22 = LCELL( _EQ006);
_EQ006 = !D0 & D1 & !D4
# D0 & !D1 & !D4
# D0 & D1 & D4
# !D0 & !D1 & D4;
-- Node name is '|fec-1:18|8and:25|:38' = '|fec-1:18|8and:25|OUT'
-- Equation name is '_LC4_F22', type is buried
_LC4_F22 = LCELL( _EQ007);
_EQ007 = !D5 & !D7 & _LC8_F22
# D5 & !D7 & !_LC8_F22
# D5 & D7 & _LC8_F22
# !D5 & D7 & !_LC8_F22;
-- Node name is '|fec-1:18|8and:25|~38~1' = '|fec-1:18|8and:25|OUT~1'
-- Equation name is '_LC8_F22', type is buried
-- synthesized logic cell
_LC8_F22 = LCELL( _EQ008);
_EQ008 = !D2 & D3 & !D6
# D2 & !D3 & !D6
# D2 & D3 & D6
# !D2 & !D3 & D6;
Project Information d:\maxplus\max2work\tran\fec.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,760K
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