count24.v

来自「在Maxplus软件平台开发的」· Verilog 代码 · 共 23 行

module count24(clk,clr,out,c);
    input     clk,clr;
    output[4:0]    out;
    output         c ;
    reg[4:0]       out;
    reg            c ;
        always @(posedge clk or negedge clr)
           begin
             if(!clr)
              begin
                out = 0;
                c   = 1;
              end
             else 
               if(out==23)
                out = out + 1;
                   else 
                      out = 0;
                      c   = 0;
           end
endmodule