📄 24count.rpt
字号:
24count
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - F 18 OR2 s 0 3 0 1 ~46~1
- 2 - F 18 OR2 0 3 1 0 :46
- 4 - F 18 DFFE + 0 0 1 3 |74161:19|f74161:sub|QA (|74161:19|f74161:sub|:9)
- 5 - F 18 AND2 0 2 0 3 |74161:19|f74161:sub|:84
- 1 - F 18 DFFE + 0 1 1 2 |74161:19|f74161:sub|QB (|74161:19|f74161:sub|:87)
- 7 - F 18 DFFE + 0 1 1 3 |74161:19|f74161:sub|QC (|74161:19|f74161:sub|:99)
- 3 - F 18 DFFE + 0 2 1 2 |74161:19|f74161:sub|QD (|74161:19|f74161:sub|:110)
- 6 - F 18 DFFE + 0 3 1 1 |74161:20|f74161:sub|QA (|74161:20|f74161:sub|:9)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\work\20\tran\24count.rpt
24count
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 3/ 96( 3%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\work\20\tran\24count.rpt
24count
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 CLK
Device-Specific Information: e:\work\20\tran\24count.rpt
24count
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 /CLR
Device-Specific Information: e:\work\20\tran\24count.rpt
24count
** EQUATIONS **
CLK : INPUT;
/CLR : INPUT;
-- Node name is 'AD0'
-- Equation name is 'AD0', type is output
AD0 = _LC4_F18;
-- Node name is 'AD1'
-- Equation name is 'AD1', type is output
AD1 = _LC1_F18;
-- Node name is 'AD2'
-- Equation name is 'AD2', type is output
AD2 = _LC7_F18;
-- Node name is 'AD3'
-- Equation name is 'AD3', type is output
AD3 = _LC3_F18;
-- Node name is 'AD5'
-- Equation name is 'AD5', type is output
AD5 = _LC6_F18;
-- Node name is '|74161:19|f74161:sub|:9' = '|74161:19|f74161:sub|QA'
-- Equation name is '_LC4_F18', type is buried
_LC4_F18 = DFFE(!_LC4_F18, GLOBAL( CLK), GLOBAL( /CLR), VCC, VCC);
-- Node name is '|74161:19|f74161:sub|:87' = '|74161:19|f74161:sub|QB'
-- Equation name is '_LC1_F18', type is buried
_LC1_F18 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL( /CLR), VCC, VCC);
_EQ001 = !_LC1_F18 & _LC4_F18
# _LC1_F18 & !_LC4_F18;
-- Node name is '|74161:19|f74161:sub|:99' = '|74161:19|f74161:sub|QC'
-- Equation name is '_LC7_F18', type is buried
_LC7_F18 = DFFE( _EQ002, GLOBAL( CLK), GLOBAL( /CLR), VCC, VCC);
_EQ002 = !_LC5_F18 & _LC7_F18
# _LC5_F18 & !_LC7_F18;
-- Node name is '|74161:19|f74161:sub|:110' = '|74161:19|f74161:sub|QD'
-- Equation name is '_LC3_F18', type is buried
_LC3_F18 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL( /CLR), VCC, VCC);
_EQ003 = _LC3_F18 & !_LC7_F18
# _LC3_F18 & !_LC5_F18
# !_LC3_F18 & _LC5_F18 & _LC7_F18;
-- Node name is '|74161:19|f74161:sub|:84'
-- Equation name is '_LC5_F18', type is buried
_LC5_F18 = LCELL( _EQ004);
_EQ004 = _LC1_F18 & _LC4_F18;
-- Node name is '|74161:20|f74161:sub|:9' = '|74161:20|f74161:sub|QA'
-- Equation name is '_LC6_F18', type is buried
_LC6_F18 = DFFE( _EQ005, GLOBAL( CLK), GLOBAL( /CLR), VCC, VCC);
_EQ005 = _LC6_F18 & !_LC7_F18
# !_LC5_F18 & _LC6_F18
# !_LC3_F18 & _LC6_F18
# _LC3_F18 & _LC5_F18 & !_LC6_F18 & _LC7_F18;
-- Node name is '/C'
-- Equation name is '/C', type is output
/C = _LC2_F18;
-- Node name is '~46~1'
-- Equation name is '~46~1', location is LC8_F18, type is buried.
-- synthesized logic cell
_LC8_F18 = LCELL( _EQ006);
_EQ006 = !_LC6_F18
# _LC1_F18
# _LC7_F18;
-- Node name is ':46'
-- Equation name is '_LC2_F18', type is buried
_LC2_F18 = LCELL( _EQ007);
_EQ007 = _LC8_F18
# !_LC3_F18
# _LC4_F18;
Project Information e:\work\20\tran\24count.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,615K
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