📄 dd_isr.s
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.module dd_isr.c
.area vector(rom, abs)
.org 40
jmp _dd_spi_i2c_isr
.org 72
jmp _dd_adf7021_sync_isr
.org 44
jmp _UART_RECV_DEAL
.org 52
jmp _UART_SEND_DEAL
.area text(rom, con, rel)
.dbfile D:\icc\examples.avr\230M\dd_isr.c
.dbfunc e dd_spi_i2c_isr _dd_spi_i2c_isr fV
; temp -> R20
.even
_dd_spi_i2c_isr::
xcall push_lset
xcall push_gset1
sbiw R28,2
.dbline -1
.dbline 16
; /*****************************************************************************
; * File: dd_isr.c
; *****************************************************************************/
;
; #include "dd.h"
; //#include "api.h"
; extern unsigned int crc16(unsigned char byte);
; extern void crc16_reset(void);
; unsigned char uart_tx_buffer[max_uart_buffer_size];
; unsigned char time_count;
; unsigned char rf_tx_state[3],crc_tempn[2];
; /*****************************************************************************
; * Function: dd_spi_i2c_isr
; ****************************************************************************/
; void dd_spi_i2c_isr(void) // 8051 vector 0x003B
; {
.dbline 24
; unsigned char temp;
; // UINT16 temp_crc;
;
; /* Handle priority processes first: SPIDAT access is extremely critical */
;
;
; // Handle SPI interrupt
; if (dd_data_port_state == DATA_PORT_TRANSMITTING)
lds R24,_dd_data_port_state
cpi R24,2
breq X0
xjmp L8
X0:
.dbline 25
; {
.dbline 27
;
; if(dd_port_data_tx_frame_idx<dd_port_data_tx_buffer[8]+9){
lds R24,_dd_port_data_tx_buffer+8
subi R24,247 ; addi 9
lds R2,_dd_port_data_tx_frame_idx
cp R2,R24
brsh L10
.dbline 27
.dbline 30
;
;
; temp = dd_port_data_tx_buffer[dd_port_data_tx_frame_idx];
ldi R24,<_dd_port_data_tx_buffer
ldi R25,>_dd_port_data_tx_buffer
mov R30,R2
clr R31
add R30,R24
adc R31,R25
ldd R20,z+0
.dbline 31
; SPDR = temp;
out 0xf,R20
.dbline 32
; if(dd_port_data_tx_frame_idx>8){
ldi R24,8
cp R24,R2
brsh L13
.dbline 32
.dbline 34
;
; crc16(temp);
mov R16,R20
xcall _crc16
.dbline 36
;
; }
L13:
.dbline 37
; dd_port_data_tx_frame_idx++;
lds R24,_dd_port_data_tx_frame_idx
subi R24,255 ; addi 1
sts _dd_port_data_tx_frame_idx,R24
.dbline 39
;
; }
xjmp L11
L10:
.dbline 40
; else{
.dbline 42
;
; if(dd_port_data_tx_frame_idx==dd_port_data_tx_buffer[8]+9){
lds R24,_dd_port_data_tx_buffer+8
subi R24,247 ; addi 9
lds R2,_dd_port_data_tx_frame_idx
cp R2,R24
brne L15
.dbline 42
.dbline 44
;
; SPDR = crc_lo;
lds R2,_crc_lo
out 0xf,R2
.dbline 45
; dd_port_data_tx_frame_idx++;
lds R24,_dd_port_data_tx_frame_idx
subi R24,255 ; addi 1
sts _dd_port_data_tx_frame_idx,R24
.dbline 47
xjmp L16
L15:
.dbline 47
;
; }else if(dd_port_data_tx_frame_idx==dd_port_data_tx_buffer[8]+10){
lds R24,_dd_port_data_tx_buffer+8
subi R24,246 ; addi 10
lds R2,_dd_port_data_tx_frame_idx
cp R2,R24
brne L18
.dbline 47
.dbline 49
;
; SPDR = crc_hi;
lds R2,_crc_hi
out 0xf,R2
.dbline 50
; dd_port_data_tx_frame_idx++;
lds R24,_dd_port_data_tx_frame_idx
subi R24,255 ; addi 1
sts _dd_port_data_tx_frame_idx,R24
.dbline 52
xjmp L19
L18:
.dbline 52
;
; }else{
.dbline 53
; dd_port_data_tx_frame_idx = 0;
clr R2
sts _dd_port_data_tx_frame_idx,R2
.dbline 54
; rf_tx_state[2]=1;
ldi R24,1
sts _rf_tx_state+2,R24
.dbline 55
; SPCR &= 0x3f;
in R24,0xd
andi R24,63
out 0xd,R24
.dbline 59
; //IEIP2 &= ~0x01;
; //SPICON &= ~0x20;
;
; }
L19:
L16:
.dbline 61
;
; }
L11:
.dbline 64
;
;
; }
L8:
.dbline 72
;
;
;
;
;
;
;
; if (dd_data_port_state == DATA_PORT_RECEIVING)
lds R24,_dd_data_port_state
cpi R24,3
breq X1
xjmp L22
X1:
.dbline 73
; {
.dbline 74
; temp = SPDR;
in R20,0xf
.dbline 77
; //SPDR = 0xFF;
;
; if(dd_port_data_rx_frame_idx==0){
lds R2,_dd_port_data_rx_frame_idx
tst R2
brne L24
.dbline 77
.dbline 79
;
; crc16(temp);
mov R16,R20
xcall _crc16
.dbline 80
; dd_port_data_rx_frame_idx++;
lds R24,_dd_port_data_rx_frame_idx
subi R24,255 ; addi 1
sts _dd_port_data_rx_frame_idx,R24
.dbline 81
; dd_port_data_rx_payload_length=temp;
sts _dd_port_data_rx_payload_length,R20
.dbline 83
;
; }
xjmp L25
L24:
.dbline 85
; //else if(dd_port_data_rx_frame_idx<(dd_port_data_rx_payload_length+1)){
; else if(dd_port_data_rx_frame_idx<6){
lds R24,_dd_port_data_rx_frame_idx
cpi R24,6
brsh L26
.dbline 85
.dbline 87
;
; dd_port_data_rx_buffer[dd_port_data_rx_frame_idx-1]=temp;
ldi R24,<_dd_port_data_rx_buffer-1
ldi R25,>_dd_port_data_rx_buffer-1
lds R30,_dd_port_data_rx_frame_idx
clr R31
add R30,R24
adc R31,R25
std z+0,R20
.dbline 88
; crc16(temp);
mov R16,R20
xcall _crc16
.dbline 89
; dd_port_data_rx_frame_idx++;
lds R24,_dd_port_data_rx_frame_idx
subi R24,255 ; addi 1
sts _dd_port_data_rx_frame_idx,R24
.dbline 90
xjmp L27
L26:
.dbline 90
; }else {
.dbline 91
; if(dd_port_data_rx_frame_idx==(dd_port_data_rx_payload_length+1)){
lds R24,_dd_port_data_rx_payload_length
subi R24,255 ; addi 1
lds R2,_dd_port_data_rx_frame_idx
cp R2,R24
brne L29
.dbline 91
.dbline 93
;
; dd_port_data_rx_buffer[dd_port_data_rx_frame_idx-1]=temp;
ldi R24,<_dd_port_data_rx_buffer-1
ldi R25,>_dd_port_data_rx_buffer-1
mov R30,R2
clr R31
add R30,R24
adc R31,R25
std z+0,R20
.dbline 94
; dd_port_data_rx_frame_idx++;
mov R24,R2
subi R24,255 ; addi 1
sts _dd_port_data_rx_frame_idx,R24
.dbline 96
;
; }
xjmp L30
L29:
.dbline 97
; else{
.dbline 98
; if((temp==crc_hi)&&(dd_port_data_rx_buffer[dd_port_data_rx_frame_idx-1]==crc_lo)){
lds R2,_crc_hi
cp R20,R2
brne L32
ldi R24,<_dd_port_data_rx_buffer-1
ldi R25,>_dd_port_data_rx_buffer-1
lds R30,_dd_port_data_rx_frame_idx
clr R31
add R30,R24
adc R31,R25
ldd R2,z+0
lds R3,_crc_lo
cp R2,R3
brne L32
.dbline 98
.dbline 100
;
; SPCR &= 0x3f; // Disable SPI,Disable I2C/SPI interrupt
in R24,0xd
andi R24,63
out 0xd,R24
.dbline 102
; //dd_has_received_whole_frame = TRUE;
; uart_tx_payload_length=dd_port_data_rx_payload_length;
lds R2,_dd_port_data_rx_payload_length
sts _uart_tx_payload_length,R2
.dbline 103
; memcpy(uart_tx_buffer,&dd_port_data_rx_buffer[0], uart_tx_payload_length);
clr R3
std y+1,R3
std y+0,R2
ldi R18,<_dd_port_data_rx_buffer
ldi R19,>_dd_port_data_rx_buffer
ldi R16,<_uart_tx_buffer
ldi R17,>_uart_tx_buffer
xcall _memcpy
.dbline 104
; uart_buffer_tx_idx=0;
clr R2
sts _uart_buffer_tx_idx,R2
.dbline 105
; UDR = uart_tx_buffer[uart_buffer_tx_idx++];
clr R3
mov R24,R2
subi R24,255 ; addi 1
sts _uart_buffer_tx_idx,R24
ldi R24,<_uart_tx_buffer
ldi R25,>_uart_tx_buffer
mov R30,R2
clr R31
add R30,R24
adc R31,R25
ldd R2,z+0
out 0xc,R2
.dbline 106
; }
L32:
.dbline 111
;
;
;
;
; }
L30:
.dbline 113
;
; }
L27:
L25:
.dbline 115
L22:
.dbline -2
.dbline 117
;
; }
;
; }
L7:
adiw R28,2
xcall pop_gset1
xcall pop_lset
.dbline 0 ; func end
reti
.dbsym r temp 20 c
.dbend
.dbfunc e dd_adf7021_sync_isr _dd_adf7021_sync_isr fV
; byte -> <dead>
; j -> <dead>
; i -> <dead>
.even
_dd_adf7021_sync_isr::
xcall push_lset
.dbline -1
.dbline 124
;
;
; /*****************************************************************************
; * Function: dd_adf7021_sync_isr
; ****************************************************************************/
; void dd_adf7021_sync_isr(void) // 8051 vector 0x0003
; {
.dbline 127
;
; unsigned char i,j,byte;
; CLI(); // Not needed if we're in an interrupt thread
cli
.dbline 130
;
;
; crc16_reset();
xcall _crc16_reset
.dbline 132
;
; SPCR |= 0x40; // Enable SPI port now for correct byte sync
sbi 0xd,6
.dbline 134
;
; crc16_reset();
xcall _crc16_reset
L36:
.dbline 137
.dbline 138
L37:
.dbline 136
;
; while((PINB&0x80)==0x80)
in R2,0x16
clr R3
sbrc R2,7
rjmp L36
L39:
.dbline 140
.dbline 141
L40:
.dbline 139
; {
; }
; while ((PINB&0x80)!=0x80)
in R24,0x16
andi R24,128
cpi R24,128
brne L39
.dbline 143
; {
; }
;
; SPCR |= 0x80; // Enable I2C/SPI interrupt
sbi 0xd,7
.dbline 146
;
; //SPDR = 0xFF;
; SPSR &= ~0x80; //to avoid the first byte 0x00;
cbi 0xe,7
.dbline 148
;
; dd_data_port_state = DATA_PORT_RECEIVING;
ldi R24,3
sts _dd_data_port_state,R24
.dbline 149
; dd_data_packet_phase = PACKET_PHASE_HEADER;
ldi R24,4
sts _dd_data_packet_phase,R24
.dbline 150
; dd_port_data_rx_frame_idx=0;
clr R2
sts _dd_port_data_rx_frame_idx,R2
.dbline -2
.dbline 153
;
; //P3 ^= 0x10;
; }
L35:
xcall pop_lset
.dbline 0 ; func end
reti
.dbsym l byte 1 c
.dbsym l j 1 c
.dbsym l i 1 c
.dbend
.dbfunc e UART_RECV_DEAL _UART_RECV_DEAL fV
; temp -> R16
.even
_UART_RECV_DEAL::
st -y,R2
st -y,R16
st -y,R24
st -y,R25
st -y,R30
st -y,R31
in R2,0x3f
st -y,R2
.dbline -1
.dbline 173
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
; void UART_RECV_DEAL (void)
;
; {
.dbline 175
; unsigned char temp;
; temp=UDR;
in R16,0xc
.dbline 176
; uart_rx_buffer[uart_buffer_rx_idx]=temp;
ldi R24,<_uart_rx_buffer
ldi R25,>_uart_rx_buffer
lds R30,_uart_buffer_rx_idx
clr R31
add R30,R24
adc R31,R25
std z+0,R16
.dbline 179
;
;
; if(uart_buffer_rx_idx>=max_uart_buffer_size){
lds R24,_uart_buffer_rx_idx
cpi R24,100
brlo L43
.dbline 179
.dbline 181
;
; uart_buffer_rx_idx=0;
clr R2
sts _uart_buffer_rx_idx,R2
.dbline 183
;
; }
L43:
.dbline 185
;
; time_count=0;
clr R2
sts _time_count,R2
.dbline -2
.dbline 187
;
; }
L42:
ld R2,y+
out 0x3f,R2
ld R31,y+
ld R30,y+
ld R25,y+
ld R24,y+
ld R16,y+
ld R2,y+
.dbline 0 ; func end
reti
.dbsym r temp 16 c
.dbend
.dbfunc e UART_SEND_DEAL _UART_SEND_DEAL fV
.even
_UART_SEND_DEAL::
st -y,R2
st -y,R3
st -y,R24
st -y,R25
st -y,R30
st -y,R31
in R2,0x3f
st -y,R2
.dbline -1
.dbline 191
.dbline 192
lds R2,_uart_tx_payload_length
lds R3,_uart_buffer_tx_idx
cp R3,R2
brsh L46
.dbline 193
.dbline 194
mov R2,R3
clr R3
mov R24,R2
subi R24,255 ; addi 1
sts _uart_buffer_tx_idx,R24
ldi R24,<_uart_tx_buffer
ldi R25,>_uart_tx_buffer
mov R30,R2
clr R31
add R30,R24
adc R31,R25
ldd R2,z+0
out 0xc,R2
.dbline 195
L46:
.dbline -2
.dbline 197
;
; void UART_SEND_DEAL (void)
;
; {
; if (uart_buffer_tx_idx < uart_tx_payload_length)
; {
; UDR = uart_tx_buffer[uart_buffer_tx_idx++];
; }
;
; }
L45:
ld R2,y+
out 0x3f,R2
ld R31,y+
ld R30,y+
ld R25,y+
ld R24,y+
ld R3,y+
ld R2,y+
.dbline 0 ; func end
reti
.dbend
.dbfunc e USART_Init _USART_Init fV
.even
_USART_Init::
.dbline -1
.dbline 218
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
; void USART_Init(void)
; {
.dbline 221
; /* 设置波特率*/
; //CLI();
; UBRRH = 0;
clr R2
out 0x20,R2
.dbline 222
; UBRRL = 0x33;
ldi R24,51
out 0x9,R24
.dbline 225
; /* 接收器与发送器使能*/
;
; UCSRB = (1<<RXEN)|(1<<TXEN);
ldi R24,24
out 0xa,R24
.dbline 227
; /* 设置帧格式: 8 个数据位, 2 个停止位*/
; UCSRC = 0xa6;
ldi R24,166
out 0x20,R24
.dbline 228
; UCSRA = 0;
out 0xb,R2
.dbline 229
; UCSRB |= (1<<RXCIE)|(1<<TXCIE);
in R24,0xa
ori R24,192
out 0xa,R24
.dbline -2
.dbline 232
; //SEI();
;
; }
L48:
.dbline 0 ; func end
ret
.dbend
.dbfunc e timer1_init _timer1_init fV
.even
_timer1_init::
.dbline -1
.dbline 236
;
; //timer 1初始化
; void timer1_init (void)
; {
.dbline 237
; TCCR1B=0x00;
clr R2
out 0x2e,R2
.dbline 238
; TCCR1A=0x00;
out 0x2f,R2
.dbline 239
; TIFR=0x00;
out 0x38,R2
.dbline 240
; TIMSK=0x00;
out 0x39,R2
.dbline 241
; OCR1A=0x4d88;
ldi R24,19848
ldi R25,77
out 0x2b,R25
out 0x2a,R24
.dbline 243
; //OCR1A=0x4d88;
; TCNT1=0x00;
clr R3
out 0x2d,R3
out 0x2c,R2
.dbline 244
; TIMSK=0x10;
ldi R24,16
out 0x39,R24
.dbline 245
; TCCR1B=0x00;
out 0x2e,R2
.dbline -2
.dbline 246
; }
L49:
.dbline 0 ; func end
ret
.dbend
.area bss(ram, con, rel)
.dbfile D:\icc\examples.avr\230M\dd_isr.c
_crc_tempn::
.blkb 2
.dbsym e crc_tempn _crc_tempn A[2:2]c
_uart_tx_buffer::
.blkb 100
.dbsym e uart_tx_buffer _uart_tx_buffer A[100:100]c
_time_count::
.blkb 1
.dbsym e time_count _time_count c
_rf_tx_state::
.blkb 3
.dbsym e rf_tx_state _rf_tx_state A[3:3]c
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