main.s

ADI公司射频芯片7020＋ATMEGA16射频模块源程序

	ldi R24,1
	sts _rf_tx_state,R24
	.dbline 84
; 			#else
; 			rf_tx_state[0] = 0;
; 			rf_tx_state[1] = 1;
; 			rf_tx_state[2] = 1;
; 			
; 			#endif
; 			//rf_tx_state[2]=0;
; 	    }
L23:
	.dbline 87
L10:
	.dbline 43
	xjmp L9
X1:
	.dbline -2
	.dbline 91
; 
; 		
; 	}
; 
; //	for(;;)	{my_delay(10000);	P3 ^= 0x10;	}
; 
; }
L7:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e transmit_constant_frame _transmit_constant_frame fV
;           byte -> <dead>
;              i -> <dead>
;              j -> <dead>
;    delay_count -> R20,R21
	.even
_transmit_constant_frame::
	xcall push_gset3
	.dbline -1
	.dbline 103
; 
; 
; 
; /*****************************************************************************
; Function:    		transmit_constant_frame
; ==============================================================================
; Description:
; 	Transmit a frame including preamble & sync word, payload length, 
; 	payload and CRC
; *****************************************************************************/
; void transmit_constant_frame(void)
; {
	.dbline 112
; 	// prepare tx frame header including preamble, sync word, payload length; the following is just an example
; 	
; 	
; 	//mac_tx_packet_header.seq_number = 0x0FF4;
; 	//mac_tx_packet_header.short_address = 0xAA;
; 	//mac_tx_packet_header.payload_length = uart_rx_rf_tx_count;
; 	unsigned int  delay_count;
; 	unsigned char j,i,byte;
; 	dd_set_ADF7021_Power_off();
	xcall _dd_set_ADF7021_Power_off
	.dbline 113
; 	delay_count=0x8ff;
	ldi R20,2303
	ldi R21,8
	.dbline 114
; 	PORTA |= 1<<RFMD_EN;
	sbi 0x1b,6
	.dbline 115
; 	DDRB  |= 1<<SPI_MISO;
	sbi 0x17,6
	.dbline 116
; 	PORTB |= 1<<SPI_MISO;
	sbi 0x18,6
L27:
	.dbline 118
	.dbline 120
L28:
	.dbline 117
; 	while(delay_count-->0)
	movw R2,R20
	subi R20,1
	sbci R21,0
	tst R2
	brne L27
	tst R3
	brne L27
X2:
	.dbline 126
; 	{
; 	
; 	}
; 	
;     
; 	
; 	// prepare payload length
; 	//0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0x12, 0x34, 0x56
; 	dd_port_data_tx_buffer[0]=0xAA;
	ldi R24,170
	sts _dd_port_data_tx_buffer,R24
	.dbline 127
; 	dd_port_data_tx_buffer[1]=0xAA;
	sts _dd_port_data_tx_buffer+1,R24
	.dbline 128
; 	dd_port_data_tx_buffer[2]=0xAA;
	sts _dd_port_data_tx_buffer+2,R24
	.dbline 129
; 	dd_port_data_tx_buffer[3]=0xAA;
	sts _dd_port_data_tx_buffer+3,R24
	.dbline 130
; 	dd_port_data_tx_buffer[4]=0xAA;
	sts _dd_port_data_tx_buffer+4,R24
	.dbline 131
; 	dd_port_data_tx_buffer[5]=0x12;
	ldi R24,18
	sts _dd_port_data_tx_buffer+5,R24
	.dbline 132
; 	dd_port_data_tx_buffer[6]=0x34;
	ldi R24,52
	sts _dd_port_data_tx_buffer+6,R24
	.dbline 133
; 	dd_port_data_tx_buffer[7]=0x56;
	ldi R24,86
	sts _dd_port_data_tx_buffer+7,R24
	.dbline 135
; 	#if tx_never
; 	dd_port_data_tx_buffer[8]=0x09;
	ldi R24,9
	sts _dd_port_data_tx_buffer+8,R24
	.dbline 136
; 	dd_port_data_tx_buffer[9]=0x55;
	ldi R24,85
	sts _dd_port_data_tx_buffer+9,R24
	.dbline 137
;     dd_port_data_tx_buffer[10]=0x55;
	sts _dd_port_data_tx_buffer+10,R24
	.dbline 138
; 	dd_port_data_tx_buffer[11]=0x55;
	sts _dd_port_data_tx_buffer+11,R24
	.dbline 139
; 	dd_port_data_tx_buffer[12]=0x76;
	ldi R24,118
	sts _dd_port_data_tx_buffer+12,R24
	.dbline 140
; 	dd_port_data_tx_buffer[13]=0x54;
	ldi R24,84
	sts _dd_port_data_tx_buffer+13,R24
	.dbline 141
; 	dd_port_data_tx_buffer[14]=0x32;
	ldi R24,50
	sts _dd_port_data_tx_buffer+14,R24
	.dbline 142
; 	dd_port_data_tx_buffer[15]=0x07;
	ldi R24,7
	sts _dd_port_data_tx_buffer+15,R24
	.dbline 143
;     dd_port_data_tx_buffer[16]=0x09;
	ldi R24,9
	sts _dd_port_data_tx_buffer+16,R24
	.dbline 144
; 	dd_port_data_tx_buffer[17]=0x09;
	sts _dd_port_data_tx_buffer+17,R24
	.dbline 151
; 	#else
; 	dd_port_data_tx_buffer[8]=uart_rx_rf_tx_count;
; 	memcpy(&dd_port_data_tx_buffer[9], uart_rx_buffer, uart_rx_rf_tx_count);
; 	#endif
; 	//memcpy(&dd_port_data_tx_buffer[9], uart_rx_buffer, uart_rx_rf_tx_count);
;     
; 	dd_set_ADF7021_Power_on();
	xcall _dd_set_ADF7021_Power_on
	.dbline 153
; 
; 	if (has_set_tx_mode_before == 1 & phy_state == PHY_IN_RX_MODE)	dd_set_RX_to_TX_mode();
	lds R24,_has_set_tx_mode_before
	cpi R24,1
	brne L49
	ldi R24,1
	ldi R25,0
	movw R10,R24
	xjmp L50
L49:
	clr R10
	clr R11
L50:
	lds R24,_phy_state
	cpi R24,3
	brne L51
	ldi R22,1
	ldi R23,0
	xjmp L52
L51:
	clr R22
	clr R23
L52:
	movw R2,R10
	and R2,R22
	and R3,R23
	tst R2
	brne X3
	tst R3
	breq L47
X3:
	.dbline 153
	xcall _dd_set_RX_to_TX_mode
	xjmp L48
L47:
	.dbline 154
; 	else dd_set_TX_mode();
	xcall _dd_set_TX_mode
L48:
	.dbline 156
; 
;     CLI(); 		
	cli
	.dbline 158
; 
;     dd_data_port_state = DATA_PORT_TRANSMITTING;
	ldi R24,2
	sts _dd_data_port_state,R24
	.dbline 159
;     dd_data_packet_phase = PACKET_PHASE_PREAMBLE;
	sts _dd_data_packet_phase,R24
	.dbline 160
; 	crc16_reset();
	xcall _crc16_reset
	.dbline 162
; 	
; 	SPCR  |= 0x80;          // Enable I2C/SPI interrupt	
	sbi 0xd,7
	.dbline 168
;   
; 	
;         
; 	
; 	/* Enable SPI  */
; 	SPCR  |= 0x40;
	sbi 0xd,6
	.dbline 171
; 
; 	//p_mac_active_tx_frame = &mac_preamble_syncword[0];
; 	dd_port_data_tx_frame_idx = 1;
	ldi R24,1
	sts _dd_port_data_tx_frame_idx,R24
	.dbline 173
;     //SBUF = p_mac_active_tx_frame[dd_port_data_tx_frame_idx]; 
; 	SPDR = dd_port_data_tx_buffer[dd_port_data_tx_frame_idx];
	ldi R24,<_dd_port_data_tx_buffer
	ldi R25,>_dd_port_data_tx_buffer
	lds R30,_dd_port_data_tx_frame_idx
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	out 0xf,R2
	.dbline 174
; 	dd_port_data_tx_frame_idx++;
	lds R24,_dd_port_data_tx_frame_idx
	subi R24,255    ; addi 1
	sts _dd_port_data_tx_frame_idx,R24
	.dbline 176
; 	
; 	delay_count=0x8ff;
	ldi R20,2303
	ldi R21,8
L53:
	.dbline 178
	.dbline 180
L54:
	.dbline 177
; 	while(delay_count-->0)
	movw R2,R20
	subi R20,1
	sbci R21,0
	tst R2
	brne L53
	tst R3
	brne L53
X4:
	.dbline 181
; 	{
; 	
; 	}
; 	dd_set_ADF7021_Power_off();
	xcall _dd_set_ADF7021_Power_off
	.dbline 184
; 	
; 	#if  tx_never
;     my_delay_1(0xffff);
	ldi R16,65535
	ldi R17,255
	xcall _my_delay_1
	.dbline 185
; 	uart_rx_rf_tx_count=9;
	ldi R24,9
	sts _uart_rx_rf_tx_count,R24
	.dbline 188
; 	#endif
; 	
;     SEI();
	sei
	.dbline -2
	.dbline 189
; }
L26:
	xcall pop_gset3
	.dbline 0 ; func end
	ret
	.dbsym l byte 1 c
	.dbsym l i 1 c
	.dbsym l j 1 c
	.dbsym r delay_count 20 i
	.dbend
	.dbfunc e receive_constant_frame _receive_constant_frame fV
	.even
_receive_constant_frame::
	xcall push_gset2
	.dbline -1
	.dbline 199
; 
; /*****************************************************************************
; Function:    		receive_constant_frame
; ==============================================================================
; Description:
; 	Receive a frame including preamble & sync word, payload length, 
; 	payload and CRC
; *****************************************************************************/
; void receive_constant_frame(void)
; { 
	.dbline 200
; 	CLI();
	cli
	.dbline 202
; 
; 	dd_set_ADF7021_Power_on();
	xcall _dd_set_ADF7021_Power_on
	.dbline 203
; 	if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE)	dd_set_TX_to_RX_mode();
	lds R24,_has_set_rx_mode_before
	cpi R24,1
	brne L59
	ldi R22,1
	ldi R23,0
	xjmp L60
L59:
	clr R22
	clr R23
L60:
	lds R24,_phy_state
	cpi R24,4
	brne L61
	ldi R20,1
	ldi R21,0
	xjmp L62
L61:
	clr R20
	clr R21
L62:
	movw R2,R22
	and R2,R20
	and R3,R21
	tst R2
	brne X5
	tst R3
	breq L57
X5:
	.dbline 203
	xcall _dd_set_TX_to_RX_mode
	xjmp L58
L57:
	.dbline 204
;     else dd_set_RX_mode();
	xcall _dd_set_RX_mode
L58:
	.dbline 206
; 
;     GICR|=0x20;            // Enable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
	in R24,0x3b
	ori R24,32
	out 0x3b,R24
	.dbline 208
; 
; 	SEI();
	sei
	.dbline -2
	.dbline 210
; 
; }
L56:
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e crc16_reset _crc16_reset fV
	.even
_crc16_reset::
	.dbline -1
	.dbline 214
; 
; 
; void crc16_reset(void)
; {
	.dbline 215
;     crc_lo = crc_hi = 0;
	clr R2
	sts _crc_hi,R2
	sts _crc_lo,R2
	.dbline -2
	.dbline 216
; }
L63:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e crc16 _crc16 fi
;    combination -> R20
;           byte -> R16
	.even
_crc16::
	xcall push_gset1
	.dbline -1
	.dbline 220
; 
; 
; unsigned int crc16(unsigned char byte)
; {
	.dbline 224
;     unsigned char combination;
; 
;     // First calculate the combination term 
;     combination = crc_lo ^ byte;
	lds R20,_crc_lo
	eor R20,R16
	.dbline 227
;  
;     // Now update the CRC register 
;     crc_lo = crc_hi ^ crc_lut_low[combination];
	ldi R24,<_crc_lut_low
	ldi R25,>_crc_lut_low
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	lpm R30,Z
	lds R2,_crc_hi
	eor R2,R30
	sts _crc_lo,R2
	.dbline 228
;     crc_hi = crc_lut_high[combination];
	ldi R24,<_crc_lut_high
	ldi R25,>_crc_lut_high
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	lpm R30,Z
	sts _crc_hi,R30
	.dbline 230
; 
;     return (crc_hi << 8) | crc_lo;
	mov R17,R30
	mov R16,R2
	.dbline -2
L64:
	xcall pop_gset1
	.dbline 0 ; func end
	ret
	.dbsym r combination 20 c
	.dbsym r byte 16 c
	.dbend