📄 atmega16.s
字号:
.module ATMEGA16.c
.area vector(rom, abs)
.org 40
jmp _dd_spi_i2c_isr
.org 72
jmp _dd_adf7021_sync_isr
.org 44
jmp _UART_RECV_DEAL
.org 52
jmp _UART_SEND_DEAL
.area text(rom, con, rel)
.dbfile D:\icc\examples.avr\230M\ATMEGA16.c
.dbfunc e dd_initialise _dd_initialise fV
.even
_dd_initialise::
.dbline -1
.dbline 61
; //#include "api.h"
; #include "dd.h"
;
;
; void dd_initialise(void);
;
;
; SLEEP_FLAG_E sleep_flag;
; char dd_user_irq_occurred;
;
; unsigned char max_transmit_times;
; char need_keep_transmitting;
; char is_use_crystal;
; char is_ADF7021_AFC_ON;
; char is_fine_IF_filter_cal;
; char is_internal_PA_ramp_used;
; char has_set_tx_mode_before;
; char has_set_rx_mode_before;
; char dd_has_received_whole_frame;
;
;
;
;
; //for data port buffer and variable
; unsigned char dd_port_data_tx_buffer[max_port_data_buffer_size];
; unsigned char dd_port_data_rx_buffer[max_port_data_buffer_size];
; unsigned char dd_port_data_tx_frame_idx;
; unsigned char dd_port_data_rx_frame_idx;
; unsigned char dd_port_data_rx_payload_length;
; unsigned char * p_active_data_tx_buffer;
;
; DATA_PORT_STATE_E dd_data_port_state;
; PACKET_PHASE_E dd_data_packet_phase;
;
;
; unsigned char crc_lo, crc_hi;
; PHY_STATE_E phy_state;
;
;
; //for uart buffer and variable
; unsigned char uart_rx_buffer[max_uart_buffer_size];
; unsigned char uart_buffer_tx_idx;
; unsigned char uart_buffer_rx_idx;
; unsigned char * p_active_uart_buffer;
; unsigned char uart_rx_payload_length;
; unsigned char uart_tx_payload_length;
;
; UART_PORT_STATE_E dd_uart_host_state;
; UART_CMD_E dd_uart_command;
;
;
; //for mac
; struct MAC_PACKET_HEADER_T mac_tx_packet_header;
; struct MAC_PACKET_HEADER_T mac_rx_packet_header;
;
; unsigned char * p_mac_active_tx_frame;
;
; //!!!!!!!!!new
;
; void dd_initialise()
; {
.dbline 62
; CLI();
cli
.dbline 67
; //WDR();
; //WDR(); //this prevents a timout on enabling
; //WDTCR = 0x0D; //WATCHDOG ENABLED - dont forget to issue WDRs
; //WDR();
; WDR();
wdr
.dbline 69
; /* 置位 WDTOE 和 WDE*/
; WDTCR |= (1<<WDTOE) | (1<<WDE);
in R24,0x21
ori R24,24
out 0x21,R24
.dbline 71
; /* 关闭WDT */
; WDTCR = 0x00;
clr R2
out 0x21,R2
.dbline 73
;
; ACSR|=0x80;
sbi 0x8,7
.dbline 74
; DDRA =0xfD;
ldi R24,253
out 0x1a,R24
.dbline 75
; DDRB =0x4b;
ldi R24,75
out 0x17,R24
.dbline 76
; DDRC =0xc3;
ldi R24,195
out 0x14,R24
.dbline 77
; DDRD =0xf3;
ldi R24,243
out 0x11,R24
.dbline 78
; PORTA |=0xBD;
in R24,0x1b
ori R24,189
out 0x1b,R24
.dbline 79
; PORTB |=0xff;
in R24,0x18
ori R24,255
out 0x18,R24
.dbline 80
; PORTC |=0xc3;
in R24,0x15
ori R24,195
out 0x15,R24
.dbline 81
; PORTD |=0xf3;
in R24,0x12
ori R24,243
out 0x12,R24
.dbline 82
; timer1_init();
xcall _timer1_init
.dbline 83
; USART_Init();
xcall _USART_Init
.dbline 85
; //RF_spi_INIT();
; GIFR=0;
clr R2
out 0x3a,R2
.dbline 86
; MCUCR =0x0a;
ldi R24,10
out 0x35,R24
.dbline 87
; MCUCSR|=0x40;
in R24,0x34
ori R24,64
out 0x34,R24
.dbline 88
; GICR |=0x20;
in R24,0x3b
ori R24,32
out 0x3b,R24
.dbline 89
; rf_tx_state[0]=0;
sts _rf_tx_state,R2
.dbline 90
; rf_tx_state[1]=0;
sts _rf_tx_state+1,R2
.dbline 91
; rf_tx_state[2]=0;
sts _rf_tx_state+2,R2
.dbline 93
;
; max_transmit_times = 0;
sts _max_transmit_times,R2
.dbline 94
; need_keep_transmitting = FALSE;
sts _need_keep_transmitting,R2
.dbline 95
; dd_uart_command = HOST_CMD_IDLE;
sts _dd_uart_command,R2
.dbline 97
;
; is_use_crystal = FALSE;
sts _is_use_crystal,R2
.dbline 98
; is_ADF7021_AFC_ON = FALSE;
sts _is_ADF7021_AFC_ON,R2
.dbline 99
; is_fine_IF_filter_cal = TRUE;
ldi R24,1
sts _is_fine_IF_filter_cal,R24
.dbline 100
; is_internal_PA_ramp_used = TRUE;
sts _is_internal_PA_ramp_used,R24
.dbline 101
; dd_set_ADF7021_Power_off();
xcall _dd_set_ADF7021_Power_off
.dbline 103
;
; dd_idle();
xcall _dd_idle
.dbline 105
;
; SEI();
sei
.dbline -2
.dbline 110
;
;
;
;
; }
L7:
.dbline 0 ; func end
ret
.dbend
.dbfunc e dd_idle _dd_idle fV
.even
_dd_idle::
.dbline -1
.dbline 115
;
;
;
; void dd_idle()
; {
.dbline 117
;
; GICR &= 0x20; // Disable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
in R24,0x3b
andi R24,32
out 0x3b,R24
.dbline 118
; SPCR &= ~0x80; // Disable I2C/SPI interrupt
cbi 0xd,7
.dbline 122
; //SPI初始化
; //SPICON = 0x0E; // SPI Slave, CPOL=1, CPHA=1. Leave disabled.
; //SPICON &= ~0x20;
; SPCR=0x0e;
ldi R24,14
out 0xd,R24
.dbline 124
;
; sleep_flag = AWAKE;
ldi R24,1
sts _sleep_flag,R24
.dbline 125
; dd_user_irq_occurred = FALSE;
clr R2
sts _dd_user_irq_occurred,R2
.dbline 128
;
; //Initialise extern variable
; dd_data_port_state = DATA_PORT_IDLE;
sts _dd_data_port_state,R24
.dbline 129
; dd_data_packet_phase = PACKET_PHASE_IDLE;
sts _dd_data_packet_phase,R24
.dbline 130
; uart_buffer_tx_idx = 0;
sts _uart_buffer_tx_idx,R2
.dbline 131
; uart_buffer_rx_idx = 0;
sts _uart_buffer_rx_idx,R2
.dbline 132
; dd_port_data_rx_payload_length = 0;
sts _dd_port_data_rx_payload_length,R2
.dbline 133
; p_active_uart_buffer = 0;
clr R3
sts _p_active_uart_buffer+1,R3
sts _p_active_uart_buffer,R2
.dbline 134
; dd_uart_host_state = UART_PORT_RECEIVING;
ldi R24,3
sts _dd_uart_host_state,R24
.dbline 136
;
; uart_rx_payload_length = UART_PAYLOAD_LENGTH;
ldi R24,252
sts _uart_rx_payload_length,R24
.dbline 137
; PORTA &= ~(1<<RFMD_EN);
cbi 0x1b,6
.dbline -2
.dbline 138
; }
L10:
.dbline 0 ; func end
ret
.dbend
.dbfunc e dd_short_delay _dd_short_delay fV
; count -> R16
.even
_dd_short_delay::
.dbline -1
.dbline 152
;
;
; /*****************************************************************************
; * Function: dd_short_delay
; * Parameters: Number of units to wait (1 unit = 256/Fcore = 1/24576)
; * Returns: Nothing
; * ===========================================================================
; * Description:
; * Short delay function based on high byte of timer 0
; * (Timer 0 must be configured as a 16 bit timer clocked at CPU core rate)
; * Max delay = 10.4ms
; ****************************************************************************/
; void dd_short_delay(unsigned char count)
; {
xjmp L13
L12:
.dbline 154
.dbline 155
nop
.dbline 156
nop
.dbline 157
nop
.dbline 158
nop
.dbline 159
nop
.dbline 160
nop
.dbline 161
nop
.dbline 162
nop
.dbline 163
nop
.dbline 164
nop
.dbline 165
nop
.dbline 166
nop
.dbline 167
nop
.dbline 168
nop
.dbline 169
nop
.dbline 170
nop
.dbline 171
nop
.dbline 172
nop
.dbline 173
nop
.dbline 174
nop
.dbline 176
L13:
.dbline 153
; while (count-- >0)
mov R2,R16
clr R3
subi R16,1
clr R4
cp R4,R2
brlo L12
.dbline -2
.dbline 178
; {
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
;
; }
;
; }
L11:
.dbline 0 ; func end
ret
.dbsym r count 16 c
.dbend
.dbfunc e my_delay _my_delay fV
; length -> y+4
.even
_my_delay::
xcall push_arg4
xcall push_gset2
.dbline -1
.dbline 181
;
; void my_delay(long length)
; {
xjmp L17
L16:
.dbline 182
ldi R20,1
ldi R21,0
ldi R22,0
ldi R23,0
movw R30,R28
ldd R2,z+4
ldd R3,z+5
ldd R4,z+6
ldd R5,z+7
sub R2,R20
sbc R3,R21
sbc R4,R22
sbc R5,R23
movw R30,R28
std z+4,R2
std z+5,R3
std z+6,R4
std z+7,R5
L17:
.dbline 182
; while (length >=0) length--;
ldi R20,0
ldi R21,0
ldi R22,0
ldi R23,0
movw R30,R28
ldd R2,z+4
ldd R3,z+5
ldd R4,z+6
ldd R5,z+7
cp R2,R20
cpc R3,R21
cpc R4,R22
cpc R5,R23
brge L16
.dbline -2
.dbline 183
; }
L15:
xcall pop_gset2
adiw R28,4
.dbline 0 ; func end
ret
.dbsym l length 4 L
.dbend
.dbfunc e my_delay_1 _my_delay_1 fV
; length -> R16,R17
.even
_my_delay_1::
.dbline -1
.dbline 187
;
;
; void my_delay_1(unsigned int length)
; {
xjmp L21
L20:
.dbline 189
.dbline 190
nop
.dbline 191
nop
.dbline 192
nop
.dbline 193
nop
.dbline 194
nop
.dbline 195
nop
.dbline 196
nop
.dbline 197
nop
.dbline 198
nop
.dbline 199
nop
.dbline 200
nop
.dbline 201
nop
.dbline 202
nop
.dbline 203
nop
.dbline 204
nop
.dbline 205
nop
.dbline 206
nop
.dbline 207
nop
.dbline 208
nop
.dbline 209
nop
.dbline 211
L21:
.dbline 188
; while (length-- >0)
movw R2,R16
subi R16,1
sbci R17,0
tst R2
brne L20
tst R3
brne L20
X0:
.dbline -2
.dbline 212
; {
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
; _NOP();
;
; }
; }
L19:
.dbline 0 ; func end
ret
.dbsym r length 16 i
.dbend
.dbfunc e dd_data_port_rx_handler _dd_data_port_rx_handler fV
.even
_dd_data_port_rx_handler::
.dbline -1
.dbline 222
;
;
;
; /*****************************************************************************
; Data Functions
; ****************************************************************************/
;
;
; void dd_data_port_rx_handler(void)
; {
.dbline 223
; dd_port_data_tx_frame_idx = 0;
clr R2
sts _dd_port_data_tx_frame_idx,R2
.dbline 224
; dd_port_data_rx_payload_length = 0;
sts _dd_port_data_rx_payload_length,R2
.dbline 225
; dd_data_port_state = DATA_PORT_IDLE;
ldi R24,1
sts _dd_data_port_state,R24
.dbline 226
; dd_data_packet_phase = PACKET_PHASE_IDLE;
sts _dd_data_packet_phase,R24
.dbline 227
; dd_has_received_whole_frame = FALSE;
sts _dd_has_received_whole_frame,R2
.dbline -2
.dbline 236
;
; //if crc_lo and crc_hi are now both zero, it manifests that data has been received correctly
; #if 0
; my_delay(100);
; SBUF = crc_lo;
; my_delay(100);
; SBUF = crc_hi;
; #endif
; }
L23:
.dbline 0 ; func end
ret
.dbend
.dbfunc e dd_uart_port_tx _dd_uart_port_tx fV
; tx_number -> R18
; p_buffer -> R16,R17
.even
_dd_uart_port_tx::
.dbline -1
.dbline 244
;
;
;
; /*****************************************************************************
; Uart Functions
; ****************************************************************************/
; void dd_uart_port_tx(unsigned char * p_buffer, unsigned char tx_number)
; {
.dbline 246
;
; dd_uart_host_state = UART_PORT_TRANSMITTING;
ldi R24,2
sts _dd_uart_host_state,R24
.dbline 248
;
; uart_tx_payload_length = tx_number;
sts _uart_tx_payload_length,R18
.dbline 249
; uart_buffer_tx_idx = 0;
clr R2
sts _uart_buffer_tx_idx,R2
.dbline 250
; p_active_uart_buffer = p_buffer;
sts _p_active_uart_buffer+1,R17
sts _p_active_uart_buffer,R16
.dbline 251
; UDR = p_active_uart_buffer[uart_buffer_tx_idx++];
clr R3
mov R24,R2
subi R24,255 ; addi 1
sts _uart_buffer_tx_idx,R24
mov R30,R2
clr R31
add R30,R16
adc R31,R17
ldd R2,z+0
out 0xc,R2
.dbline 253
;
; SEI();
sei
.dbline -2
.dbline 255
;
; }
L24:
.dbline 0 ; func end
ret
.dbsym r tx_number 18 c
.dbsym r p_buffer 16 pc
.dbend
.area bss(ram, con, rel)
.dbfile D:\icc\examples.avr\230M\ATMEGA16.c
_crc_hi::
.blkb 1
.dbsym e crc_hi _crc_hi c
_crc_lo::
.blkb 1
.dbsym e crc_lo _crc_lo c
_p_mac_active_tx_frame::
.blkb 2
.dbsym e p_mac_active_tx_frame _p_mac_active_tx_frame pc
_mac_tx_packet_header::
.blkb 4
.dbstruct 0 4 MAC_PACKET_HEADER_T
.dbfield 0 seq_number i
.dbfield 2 short_address c
.dbfield 3 payload_length c
.dbend
.dbsym e mac_tx_packet_header _mac_tx_packet_header S[MAC_PACKET_HEADER_T]
_mac_rx_packet_header::
.blkb 4
.dbsym e mac_rx_packet_header _mac_rx_packet_header S[MAC_PACKET_HEADER_T]
_phy_state::
.blkb 1
.dbsym e phy_state _phy_state c
_dd_uart_command::
.blkb 1
.dbsym e dd_uart_command _dd_uart_command c
_dd_uart_host_state::
.blkb 1
.dbsym e dd_uart_host_state _dd_uart_host_state c
_uart_tx_payload_length::
.blkb 1
.dbsym e uart_tx_payload_length _uart_tx_payload_length c
_uart_rx_payload_length::
.blkb 1
.dbsym e uart_rx_payload_length _uart_rx_payload_length c
_p_active_uart_buffer::
.blkb 2
.dbsym e p_active_uart_buffer _p_active_uart_buffer pc
_uart_buffer_rx_idx::
.blkb 1
.dbsym e uart_buffer_rx_idx _uart_buffer_rx_idx c
_uart_buffer_tx_idx::
.blkb 1
.dbsym e uart_buffer_tx_idx _uart_buffer_tx_idx c
_uart_rx_buffer::
.blkb 100
.dbsym e uart_rx_buffer _uart_rx_buffer A[100:100]c
_dd_data_packet_phase::
.blkb 1
.dbsym e dd_data_packet_phase _dd_data_packet_phase c
_dd_data_port_state::
.blkb 1
.dbsym e dd_data_port_state _dd_data_port_state c
_p_active_data_tx_buffer::
.blkb 2
.dbsym e p_active_data_tx_buffer _p_active_data_tx_buffer pc
_dd_port_data_rx_payload_length::
.blkb 1
.dbsym e dd_port_data_rx_payload_length _dd_port_data_rx_payload_length c
_dd_port_data_rx_frame_idx::
.blkb 1
.dbsym e dd_port_data_rx_frame_idx _dd_port_data_rx_frame_idx c
_dd_port_data_tx_frame_idx::
.blkb 1
.dbsym e dd_port_data_tx_frame_idx _dd_port_data_tx_frame_idx c
_dd_port_data_rx_buffer::
.blkb 100
.dbsym e dd_port_data_rx_buffer _dd_port_data_rx_buffer A[100:100]c
_dd_port_data_tx_buffer::
.blkb 100
.dbsym e dd_port_data_tx_buffer _dd_port_data_tx_buffer A[100:100]c
_dd_has_received_whole_frame::
.blkb 1
.dbsym e dd_has_received_whole_frame _dd_has_received_whole_frame c
_has_set_rx_mode_before::
.blkb 1
.dbsym e has_set_rx_mode_before _has_set_rx_mode_before c
_has_set_tx_mode_before::
.blkb 1
.dbsym e has_set_tx_mode_before _has_set_tx_mode_before c
_is_internal_PA_ramp_used::
.blkb 1
.dbsym e is_internal_PA_ramp_used _is_internal_PA_ramp_used c
_is_fine_IF_filter_cal::
.blkb 1
.dbsym e is_fine_IF_filter_cal _is_fine_IF_filter_cal c
_is_ADF7021_AFC_ON::
.blkb 1
.dbsym e is_ADF7021_AFC_ON _is_ADF7021_AFC_ON c
_is_use_crystal::
.blkb 1
.dbsym e is_use_crystal _is_use_crystal c
_need_keep_transmitting::
.blkb 1
.dbsym e need_keep_transmitting _need_keep_transmitting c
_max_transmit_times::
.blkb 1
.dbsym e max_transmit_times _max_transmit_times c
_dd_user_irq_occurred::
.blkb 1
.dbsym e dd_user_irq_occurred _dd_user_irq_occurred c
_sleep_flag::
.blkb 1
.dbsym e sleep_flag _sleep_flag c
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