dd_adf7021._c

ADI公司射频芯片7020＋ATMEGA16射频模块源程序

#include "dd.h"
//#include "api.h"

#if  0
union ADF70XX_REG_T
    {
        unsigned long  whole_reg;
        unsigned char   byte[4];    // Warning: Be endian-specific when accessing bytes

    };
	
struct MAC_PACKET_HEADER_T
	{
	    unsigned int      seq_number;
	    unsigned char       short_address;
	    unsigned char       payload_length;
	
	};
#endif
unsigned char ADF7021_CE_SIGNAL;
#pragma data:code
const  unsigned  char gain_correction[] = 
    { 2*86, 0, 0, 0, 2*58, 2*38, 2*24, 0, 
	0, 0, 0, 0, 0, 0, 0, 0 }; // 7021
#pragma data:code

/****************************************************************************
 *                    ADF7021 Control Functions                             *
 ****************************************************************************/
 


union ADF70XX_REG_T dd_read_7021_reg(unsigned char readback_config)
{
    union ADF70XX_REG_T register_value;
    unsigned char i, j;
    unsigned char byte;


    #if  1
    /* Write readback and ADC control value */
    register_value.whole_reg = ((readback_config & 0x1F) << 4);
    register_value.whole_reg |= 7; // Address the readback setup register

    dd_write_7021_reg((unsigned char *)&register_value);

    register_value.whole_reg = 0;
    #endif

    /* Read back value */

    PORTA &= ~(1<<ADF7021_SDATA);
    PORTA &= ~(1<<ADF7021_SCLK);
    PORTA |= 1<<ADF7021_SLE;

   //Clock in first bit and discard 
    PORTA |= 1<<ADF7021_SCLK;
    byte = 0; // Slight pulse extend
    PORTA &= ~(1<<ADF7021_SCLK);


    /* Clock in data MSbit first */
    for (i=2; i<=3; i++)
    {
        for (j=8; j>0; j--)
        {
            PORTA |= 1<<ADF7021_SCLK;
            byte += byte; // left shift 1
            PORTA &= ~(1<<ADF7021_SCLK);

          if ((PINA&0x02)==0x02) byte |= 1;
        }

        register_value.byte[i] = byte;

		my_delay(1);	//wait for a bit time
	    		
	}//for i=2 : 3;

	PORTA |= 1<<ADF7021_SCLK;
	PORTA &= ~(1<<ADF7021_SCLK);

/*
	ADF7021_SCLK = 1;
	ADF7021_SCLK = 0;
*/
    PORTA &= ~(1<<ADF7021_SLE);
    // All port lines left low  

    return register_value;
}




void dd_write_7021_reg(unsigned char * reg_bytes)
{
    signed char i, j;
    unsigned char byte;

    PORTA &= ~(1<<ADF7021_SLE);
    PORTA &= ~(1<<ADF7021_SCLK);


    /* Clock data out MSbit first */

    for (i=3; i>=0; i--)

    {
        byte = reg_bytes[i];

        for (j=8; j>0; j--)
        {
            PORTA &= ~(1<<ADF7021_SCLK);
            if ((byte & 0x80)==0x80) 
			    {PORTA |= 1<<ADF7021_SDATA;}
            else 
			    {PORTA &= ~(1<<ADF7021_SDATA);}
			
			
            PORTA |= 1<<ADF7021_SCLK;
            byte += byte; // left shift 1
        }
        PORTA &= ~(1<<ADF7021_SCLK);
    }


    /* Strobe the latch */

    PORTA |= 1<<ADF7021_SLE;
    PORTA |= 1<<ADF7021_SLE; // Slight pulse extend
    PORTA &= ~(1<<ADF7021_SDATA);
    PORTA &= ~(1<<ADF7021_SLE);

    /* All port lines left low */

}


void dd_set_ADF7021_Power_on(void)
{
	if (ADF7021_CE_SIGNAL == 0)
	{
		PORTB |= 1<<ADF7021_CE;
		ADF7021_CE_SIGNAL=1;
		phy_state = PHY_POWERON;
		if ( is_use_crystal == TRUE ) 	dd_short_delay(25);	//delay 1ms
	}
}


void dd_set_ADF7021_Power_off(void)
{
	union ADF70XX_REG_T register_value;


	if ((ADF7021_CE_SIGNAL == 1) && (is_internal_PA_ramp_used == TRUE))	
	{
		register_value.whole_reg = 0x00685502;			//Ramp Rate = 16 codes/bit, close PA firstly
		dd_write_7021_reg(&register_value.byte[0]);
		dd_short_delay(100);							//delay for 4 bits
	}
    ADF7021_CE_SIGNAL = 0;
	PORTB &= ~(1<<ADF7021_CE);

	has_set_tx_mode_before = FALSE;
	has_set_rx_mode_before = FALSE;

	phy_state = PHY_DISABLED;
}


void dd_set_TX_to_RX_mode(void)
{
	union ADF70XX_REG_T register_value;

	//write R0, switch TX to RX and change LO
	register_value.whole_reg = 0x885d7ef0;
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(0);		//delay 40us

	phy_state = PHY_IN_RX_MODE;
}

void dd_set_TX_mode()
{
	union ADF70XX_REG_T register_value;

	//	for ADF7021DB2 864M

	//write R1, turn on VCO
	register_value.whole_reg = 0x21B5031;
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(38);		//delay 800us

	//write R3, turn on TX/RX clocks
	register_value.whole_reg = 0x2B1525e3;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R0, turn on PLL
	register_value.whole_reg = 0x81187cf0;
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(1);		//delay 40us

	//write R2, turn on PA
	register_value.whole_reg = 0x0067fd82;			//Ramp Rate = 16 codes/bit, TX level = 2;
//	register_value.whole_reg = 0x006FF582;			//max power TX
	dd_write_7021_reg(&register_value.byte[0]);
	if (is_internal_PA_ramp_used == TRUE)		dd_short_delay(180);	//delay for 4ms, 4 bits for DR = 1Kbps

	has_set_tx_mode_before = TRUE;
	phy_state = PHY_IN_TX_MODE;

}
void dd_set_RX_mode()
{
	union ADF70XX_REG_T register_value;

	//	for ADF7021DB2 864M

	//write R1, turn on VCO
	register_value.whole_reg = 0x00535011;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R3, turn on TX/RX clocks
	register_value.whole_reg = 0x2B1734E3;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R6 here, if fine IF filter cal is wanted


	//write R5 to start IF filter cal
	register_value.whole_reg = 0x00003155;	//write R5 to start IF filter cal
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(5);		//delay 0.2ms

	//write R11, configure sync word detect
	register_value.whole_reg = 0x091A2B3B;	//sync word = 0x123456;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R12, start sync word detect
	register_value.whole_reg = 0x0000018C;	//for sync word detect;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R0, turn on PLL
	register_value.whole_reg = 0x095F2DC0;
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(0);		//delay 40us

	//write R4, turn on demodulation
	register_value.whole_reg = 0x8016AA14;
	dd_write_7021_reg(&register_value.byte[0]);

	if (is_ADF7021_AFC_ON == TRUE)
	{
		//write R10, turn AFC on
		register_value.whole_reg = 0x3296355A;
		dd_write_7021_reg(&register_value.byte[0]);
	}

	has_set_rx_mode_before = TRUE;
	phy_state = PHY_IN_RX_MODE;

}


void dd_set_RX_to_TX_mode()
{
	union ADF70XX_REG_T register_value;

	//write R0, switch RX to TX and change LO
	register_value.whole_reg = 0x805d7ef0;
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(0);		//delay 40us

	//please confirm PA level configuration in dd_set_RX_mode(); if it is different, please re-write R2

	phy_state = PHY_IN_TX_MODE;
}

/****************************************************************************
 *                   		   readback functions                           *
 ***************************************************************************/
#if 1
void dd_read_AFC(void)
{
	union ADF70XX_REG_T uartlog;
	uartlog = dd_read_7021_reg(0x10);
	dd_uart_port_tx(&uartlog.byte[2], 2);
}





void dd_read_RSSI(void)
{
    signed int rssi = 0;
	union ADF70XX_REG_T RSSI_value;

	RSSI_value = dd_read_7021_reg(0x14);

	RSSI_value.whole_reg += RSSI_value.whole_reg ;

    rssi = RSSI_value.byte[3];
	rssi += gain_correction[RSSI_value.byte[2] & 0x0F] ;
    rssi = rssi /4 ;
	//RSSI(dBm) = rssi + 130

	dd_uart_port_tx((unsigned char *)&rssi, 2);
}



void dd_read_filter_cal(void)
{
	union ADF70XX_REG_T uartlog;

	//dd_set_ADF7021_Power_on();
	uartlog = dd_read_7021_reg(0x18);
	dd_uart_port_tx(&uartlog.byte[2], 2);
}



void dd_read_ADF70XX_version(void)
{
	union ADF70XX_REG_T uartlog;

	dd_set_ADF7021_Power_on();
	uartlog = dd_read_7021_reg(0x1C);
	//dd_uart_port_tx(&uartlog.byte[2], 2);
}


/*****************************************************************************
Function:    			dd_ADC_readback
==============================================================================
Description:
	Only used for external ADC, voltage, and temperature readback
*****************************************************************************/
void dd_ADC_readback(unsigned char R7_value)
{
	union ADF70XX_REG_T temp, ADC_readback;

	if ( phy_state == PHY_POWERON )
	{
		temp.whole_reg = 0x108;					//Enable ADC
		dd_write_7021_reg(&temp.byte[0]);

		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
	}

	if ( phy_state == PHY_IN_TX_MODE )
	{
		temp.whole_reg = 0x118;					//Enable ADC
		dd_write_7021_reg(&temp.byte[0]);

		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
	}

	if ( phy_state == PHY_IN_RX_MODE )
	{
		temp.whole_reg = 0x631E9;			//Turn off AGC
		dd_write_7021_reg(&temp.byte[0]);

		temp.whole_reg = 0x108;				//Turn on ADC
		dd_write_7021_reg(&temp.byte[0]);

		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
	}

	dd_set_ADF7021_Power_off();

	
	dd_uart_port_tx(&ADC_readback.byte[2], 2);

}
#endif

void test_mode(void)
{
	union ADF70XX_REG_T test_value,register_value;

	//	for ADF7021DB2 864M
    register_value.whole_reg = 0x000001CC;	//for sync word detect;
	dd_write_7021_reg(&register_value.byte[0]);
    #if  0
	//write R1, turn on VCO
	register_value.whole_reg = 0x80535011;
	dd_write_7021_reg(&register_value.byte[0]);
    
	//write R3, turn on TX/RX clocks
	register_value.whole_reg = 0x2B1734E3;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R6 here, if fine IF filter cal is wanted


	//write R5 to start IF filter cal
	register_value.whole_reg = 0x00003155;	//write R5 to start IF filter cal
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(5);		//delay 0.2ms

	//write R11, configure sync word detect
	register_value.whole_reg = 0x091A2B3B;	//sync word = 0x123456;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R12, start sync word detect
	register_value.whole_reg = 0x000001CC;	//for sync word detect;
	dd_write_7021_reg(&register_value.byte[0]);

	//write R0, turn on PLL
	register_value.whole_reg = 0x885d7ef0;
	dd_write_7021_reg(&register_value.byte[0]);
	dd_short_delay(0);		//delay 40us

	//write R4, turn on demodulation
	register_value.whole_reg = 0x80139A14;
	dd_write_7021_reg(&register_value.byte[0]);

	if (is_ADF7021_AFC_ON == TRUE)
	{
		//write R10, turn AFC on
		register_value.whole_reg = 0x3296355A;
		dd_write_7021_reg(&register_value.byte[0]);
	}

	has_set_rx_mode_before = TRUE;
	phy_state = PHY_IN_RX_MODE;
    #endif 
}
/* EOF */