aduc847._c

ADI公司射频芯片7020＋ATMEGA16射频模块源程序

#include <api.h>
#include <dd.h>


unsigned char code tx_frame_payload[] = {
    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
    0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
    0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F,
    0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
    0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F,
    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
    0x38,0x39 , 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F
};



unsigned char code mac_preamble_syncword[] = {
	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0x12, 0x34, 0x56};



SLEEP_FLAG_E sleep_flag;
BOOL dd_user_irq_occurred;

UINT8 max_transmit_times;
BOOL need_keep_transmitting;
BOOL is_use_crystal;
BOOL is_ADF7021_AFC_ON;
BOOL is_fine_IF_filter_cal;
BOOL is_internal_PA_ramp_used;
BOOL has_set_tx_mode_before;
BOOL has_set_rx_mode_before;
BOOL dd_has_received_whole_frame;




//for data port buffer and variable
UINT8 xdata dd_port_data_tx_buffer[max_port_data_buffer_size];
UINT8 xdata dd_port_data_rx_buffer[max_port_data_buffer_size];
UINT8 dd_port_data_tx_frame_idx;
UINT8 dd_port_data_rx_frame_idx;
UINT8 dd_port_data_rx_payload_length;
pUINT8 p_active_data_tx_buffer;

DATA_PORT_STATE_E dd_data_port_state;
PACKET_PHASE_E dd_data_packet_phase;


UINT8 crc_lo, crc_hi;
PHY_STATE_E phy_state;


//for uart buffer and variable
UINT8 xdata uart_rx_buffer[max_uart_buffer_size];
UINT8 uart_buffer_tx_idx;
UINT8 uart_buffer_rx_idx;
pUINT8 p_active_uart_buffer;
UINT8 uart_rx_payload_length;
UINT8 uart_tx_payload_length;

UART_PORT_STATE_E dd_uart_host_state;
UART_CMD_E dd_uart_command;


//for mac
MAC_PACKET_HEADER_T  mac_tx_packet_header;
MAC_PACKET_HEADER_T  mac_rx_packet_header;  

pUINT8 p_mac_active_tx_frame;			



void dd_initialise()
{

	PLLCON = 0x01;

    /* Force ports to known state/direction */
    P0 = P0_DEFAULT;
    P1 = P1_DEFAULT;
    P2 = P2_DEFAULT;
    P3 = P3_DEFAULT;


    /* Set up timers */
    TMOD = 0x11;            // Both T0 and T1 16bit cascaded
    TCON = 0x55;            // Timers running, /INT0 and /INT1 trigger type = edge

	INTERRUPTS_OFF; 
	IE  |= 0x10;			// Enable UART interrupt
 	IE  |= 0x04;			// Enable external interrupt 1

	IE &= ~0x01;             // Disable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
	IEIP2 &= ~0x01;         // Disable I2C/SPI interrupt	


	T3CON = 0x81;			//set T3CON = 0x85 and T3FD = 0x12 for 9600   when Fcore = 6.291456 MHz
  	T3FD = 0x2D;			//set T3CON = 0x81 and T3FD = 0x2D for 115200 when Fcore = 6.291456 MHz
  	SCON = 0x50;


	max_transmit_times = 0;
	need_keep_transmitting = FALSE;
	dd_uart_command = HOST_CMD_IDLE;

	is_use_crystal = FALSE;
	is_ADF7021_AFC_ON = FALSE;
	is_fine_IF_filter_cal = TRUE;
	is_internal_PA_ramp_used = TRUE;
	dd_set_ADF7021_Power_off();

	dd_idle();

	INTERRUPTS_ON;

}



void dd_idle()
{

	IE &= ~0x01;             // Disable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
	IEIP2 &= ~0x01;         // Disable I2C/SPI interrupt	

    SPICON = 0x0E;          // SPI Slave, CPOL=1, CPHA=1. Leave disabled.
	SPICON &= ~0x20;

    sleep_flag = AWAKE;
    dd_user_irq_occurred = FALSE;

	//Initialise extern variable
    dd_data_port_state = DATA_PORT_IDLE;
    dd_data_packet_phase = PACKET_PHASE_IDLE;
	uart_buffer_tx_idx = 0;
	uart_buffer_rx_idx = 0;
	dd_port_data_rx_payload_length = 0;
	p_active_uart_buffer = 0;
	dd_uart_host_state = UART_PORT_RECEIVING;

	uart_rx_payload_length = UART_PAYLOAD_LENGTH;
}


/*****************************************************************************
 * Function:    dd_short_delay
 * Parameters:  Number of units to wait (1 unit = 256/Fcore = 1/24576)
 * Returns:     Nothing
 * ===========================================================================
 * Description:
 *      Short delay function based on high byte of timer 0
 *      (Timer 0 must be configured as a 16 bit timer clocked at CPU core rate)
 *      Max delay = 10.4ms
 ****************************************************************************/
void dd_short_delay(UINT8 count)
{
    TL0 = 0;
    TH0 = 0;

    while(TH0 != count);
}



void my_delay(long length) 
{
	while (length >=0)		length--;
}



/*****************************************************************************
    				    	Data Functions
 ****************************************************************************/


void dd_data_port_rx_handler(void)		
{
	dd_port_data_tx_frame_idx = 0;
	dd_port_data_rx_payload_length = 0;
	dd_data_port_state = DATA_PORT_IDLE;
    dd_data_packet_phase = PACKET_PHASE_IDLE;
	dd_has_received_whole_frame = FALSE;

	//if crc_lo and crc_hi are now both zero, it manifests that data has been received correctly
	my_delay(100);
	SBUF = crc_lo;
	my_delay(100);
	SBUF = crc_hi;
}



/*****************************************************************************
    				    	Uart Functions
 ****************************************************************************/
void dd_uart_port_tx(pUINT8 p_buffer, UINT8 tx_number)
{

	dd_uart_host_state = UART_PORT_TRANSMITTING;

	uart_tx_payload_length = tx_number;
	uart_buffer_tx_idx = 0;
	p_active_uart_buffer = p_buffer;
	SBUF = p_active_uart_buffer[uart_buffer_tx_idx++];

    INTERRUPTS_ON;

}

/*****************************************************************************
  						   uart_rx_data_handler
/****************************************************************************/
void uart_rx_data_handler()
{

	uart_rx_buffer[uart_rx_payload_length+2] = 0xFA;

    switch (dd_uart_command )
    {
        case HOST_CMD_IDLE:
			dd_idle();
   	    break;

        case HOST_CMD_TX_FRAME:
			dd_idle();
       		transmit_constant_frame();
   	    break;

        case HOST_CMD_TX_FRAME_FOREVER_STRART:
			need_keep_transmitting = TRUE;
       		max_transmit_times = 0;
   	    break;

        case HOST_CMD_TX_FRAME_FOREVER_STOP:
			need_keep_transmitting = FALSE;
       		max_transmit_times = 0;
   	    break;

        case HOST_CMD_TX_FRAME_MAX_TIMES:
			need_keep_transmitting = FALSE;
       		max_transmit_times = uart_rx_buffer[2];
   	    break;

        case HOST_CMD_RX_FRAME:
			dd_idle();
			receive_constant_frame();
        break;

        case HOST_CMD_POWERON:
			dd_set_ADF7021_Power_on();
		break;

        case HOST_CMD_POWERDOWN:
			dd_set_ADF7021_Power_off();
        break;

        case HOST_CMD_TX_MODE:
			dd_set_ADF7021_Power_on();
			dd_set_TX_mode();
        break;

        case HOST_CMD_RX_MODE:
			dd_set_ADF7021_Power_on();
			if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE)	dd_set_TX_to_RX_mode();
		    else dd_set_RX_mode();
        break;


        case HOST_CMD_READ_AFC:
			dd_idle();
			dd_set_ADF7021_Power_on();
			if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE)	dd_set_TX_to_RX_mode();
		    else dd_set_RX_mode();
   			dd_read_AFC();
         break;

		case HOST_CMD_READ_RSSI:
			dd_idle();
 			dd_set_ADF7021_Power_on();
			if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE)	dd_set_TX_to_RX_mode();
		    else dd_set_RX_mode();
  			dd_read_RSSI();
	        break;

        case HOST_CMD_READ_BATT:
			dd_idle();
  			dd_set_ADF7021_Power_on();
  			dd_ADC_readback(0x15);
	    break;

		case HOST_CMD_READ_TEMP:
			dd_idle();
  			dd_set_ADF7021_Power_on();
  			dd_ADC_readback(0x16);
		break;

        case HOST_CMD_READ_EXT_ADC:
			dd_idle();
 			dd_set_ADF7021_Power_on();
   			dd_ADC_readback(0x17);
        break;

        case HOST_CMD_READ_FILTER:
			dd_idle();
			dd_set_ADF7021_Power_on();
			if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE)	dd_set_TX_to_RX_mode();
		    else dd_set_RX_mode();
   			dd_read_filter_cal();
        break;

        case HOST_CMD_READ_VERSION:
			dd_idle();
  			dd_read_ADF70XX_version();
		break;

	
		case HOST_CMD_LOOPBACK:
			SBUF = HOST_CMD_LOOPBACK;
			dd_uart_host_state = UART_PORT_RECEIVING;
		break;
			
		default:		
		break;
	}// switch

	dd_uart_command = HOST_CMD_IDLE;
}



/* EOF */