📄 dd_adf7021.lis
字号:
03EE 4880 ldd R4,y+0
03F0 5980 ldd R5,y+1
03F2 420C add R4,R2
03F4 531C adc R5,R3
03F6 5982 std y+1,R5
03F8 4882 std y+0,R4
03FA .dbline 307
03FA ; rssi = rssi /4 ;
03FA 24E0 ldi R18,4
03FC 30E0 ldi R19,0
03FE 8201 movw R16,R4
0400 0E940000 xcall div16s
0404 1983 std y+1,R17
0406 0883 std y+0,R16
0408 .dbline 310
0408 ; //RSSI(dBm) = rssi + 130
0408 ;
0408 ; dd_uart_port_tx((unsigned char *)&rssi, 2);
0408 22E0 ldi R18,2
040A 8E01 movw R16,R28
040C 0E940000 xcall _dd_uart_port_tx
0410 .dbline -2
0410 .dbline 311
0410 ; }
0410 L48:
0410 2696 adiw R28,6
0412 .dbline 0 ; func end
0412 0895 ret
0414 .dbsym l RSSI_value 2 S[ADF70XX_REG_T]
0414 .dbsym l rssi 0 I
0414 .dbend
0414 .dbfunc e dd_read_filter_cal _dd_read_filter_cal fV
0414 ; uartlog -> y+0
.even
0414 _dd_read_filter_cal::
0414 2497 sbiw R28,4
0416 .dbline -1
0416 .dbline 316
0416 ;
0416 ;
0416 ;
0416 ; void dd_read_filter_cal(void)
0416 ; {
0416 .dbline 320
0416 ; union ADF70XX_REG_T uartlog;
0416 ;
0416 ; //dd_set_ADF7021_Power_on();
0416 ; uartlog = dd_read_7021_reg(0x18);
0416 28E1 ldi R18,24
0418 8E01 movw R16,R28
041A F2DD xcall _dd_read_7021_reg
041C .dbline 321
041C ; dd_uart_port_tx(&uartlog.byte[2], 2);
041C 22E0 ldi R18,2
041E 8E01 movw R16,R28
0420 0E5F subi R16,254 ; offset = 2
0422 1F4F sbci R17,255
0424 0E940000 xcall _dd_uart_port_tx
0428 .dbline -2
0428 .dbline 322
0428 ; }
0428 L51:
0428 2496 adiw R28,4
042A .dbline 0 ; func end
042A 0895 ret
042C .dbsym l uartlog 0 S[ADF70XX_REG_T]
042C .dbend
042C .dbfunc e dd_read_ADF70XX_version _dd_read_ADF70XX_version fV
042C ; uartlog -> y+0
.even
042C _dd_read_ADF70XX_version::
042C 2497 sbiw R28,4
042E .dbline -1
042E .dbline 327
042E ;
042E ;
042E ;
042E ; void dd_read_ADF70XX_version(void)
042E ; {
042E .dbline 330
042E ; union ADF70XX_REG_T uartlog;
042E ;
042E ; dd_set_ADF7021_Power_on();
042E 88DE xcall _dd_set_ADF7021_Power_on
0430 .dbline 331
0430 ; uartlog = dd_read_7021_reg(0x1C);
0430 2CE1 ldi R18,28
0432 8E01 movw R16,R28
0434 E5DD xcall _dd_read_7021_reg
0436 .dbline -2
0436 .dbline 333
0436 ; //dd_uart_port_tx(&uartlog.byte[2], 2);
0436 ; }
0436 L53:
0436 2496 adiw R28,4
0438 .dbline 0 ; func end
0438 0895 ret
043A .dbsym l uartlog 0 S[ADF70XX_REG_T]
043A .dbend
043A .dbfunc e dd_ADC_readback _dd_ADC_readback fV
043A ; ADC_readback -> y+4
043A ; temp -> y+0
043A ; R7_value -> R10
.even
043A _dd_ADC_readback::
043A 0E940000 xcall push_gset3
043E A02E mov R10,R16
0440 2897 sbiw R28,8
0442 .dbline -1
0442 .dbline 343
0442 ;
0442 ;
0442 ; /*****************************************************************************
0442 ; Function: dd_ADC_readback
0442 ; ==============================================================================
0442 ; Description:
0442 ; Only used for external ADC, voltage, and temperature readback
0442 ; *****************************************************************************/
0442 ; void dd_ADC_readback(unsigned char R7_value)
0442 ; {
0442 .dbline 346
0442 ; union ADF70XX_REG_T temp, ADC_readback;
0442 ;
0442 ; if ( phy_state == PHY_POWERON )
0442 80910000 lds R24,_phy_state
0446 8230 cpi R24,2
0448 81F4 brne L55
044A .dbline 347
044A ; {
044A .dbline 348
044A ; temp.whole_reg = 0x108; //Enable ADC
044A 48E0 ldi R20,8
044C 51E0 ldi R21,1
044E 60E0 ldi R22,0
0450 70E0 ldi R23,0
0452 FE01 movw R30,R28
0454 4083 std z+0,R20
0456 5183 std z+1,R21
0458 6283 std z+2,R22
045A 7383 std z+3,R23
045C .dbline 349
045C ; dd_write_7021_reg(&temp.byte[0]);
045C 8E01 movw R16,R28
045E 48DE xcall _dd_write_7021_reg
0460 .dbline 351
0460 ;
0460 ; ADC_readback = dd_read_7021_reg(R7_value); //readback ADC value
0460 2A2D mov R18,R10
0462 8E01 movw R16,R28
0464 0C5F subi R16,252 ; offset = 4
0466 1F4F sbci R17,255
0468 CBDD xcall _dd_read_7021_reg
046A .dbline 352
046A ; }
046A L55:
046A .dbline 354
046A ;
046A ; if ( phy_state == PHY_IN_TX_MODE )
046A 80910000 lds R24,_phy_state
046E 8430 cpi R24,4
0470 81F4 brne L57
0472 .dbline 355
0472 ; {
0472 .dbline 356
0472 ; temp.whole_reg = 0x118; //Enable ADC
0472 48E1 ldi R20,24
0474 51E0 ldi R21,1
0476 60E0 ldi R22,0
0478 70E0 ldi R23,0
047A FE01 movw R30,R28
047C 4083 std z+0,R20
047E 5183 std z+1,R21
0480 6283 std z+2,R22
0482 7383 std z+3,R23
0484 .dbline 357
0484 ; dd_write_7021_reg(&temp.byte[0]);
0484 8E01 movw R16,R28
0486 34DE xcall _dd_write_7021_reg
0488 .dbline 359
0488 ;
0488 ; ADC_readback = dd_read_7021_reg(R7_value); //readback ADC value
0488 2A2D mov R18,R10
048A 8E01 movw R16,R28
048C 0C5F subi R16,252 ; offset = 4
048E 1F4F sbci R17,255
0490 B7DD xcall _dd_read_7021_reg
0492 .dbline 360
0492 ; }
0492 L57:
0492 .dbline 362
0492 ;
0492 ; if ( phy_state == PHY_IN_RX_MODE )
0492 80910000 lds R24,_phy_state
0496 8330 cpi R24,3
0498 D9F4 brne L59
049A .dbline 363
049A ; {
049A .dbline 364
049A ; temp.whole_reg = 0x631E9; //Turn off AGC
049A 49EE ldi R20,233
049C 51E3 ldi R21,49
049E 66E0 ldi R22,6
04A0 70E0 ldi R23,0
04A2 FE01 movw R30,R28
04A4 4083 std z+0,R20
04A6 5183 std z+1,R21
04A8 6283 std z+2,R22
04AA 7383 std z+3,R23
04AC .dbline 365
04AC ; dd_write_7021_reg(&temp.byte[0]);
04AC 8E01 movw R16,R28
04AE 20DE xcall _dd_write_7021_reg
04B0 .dbline 367
04B0 ;
04B0 ; temp.whole_reg = 0x108; //Turn on ADC
04B0 48E0 ldi R20,8
04B2 51E0 ldi R21,1
04B4 60E0 ldi R22,0
04B6 70E0 ldi R23,0
04B8 FE01 movw R30,R28
04BA 4083 std z+0,R20
04BC 5183 std z+1,R21
04BE 6283 std z+2,R22
04C0 7383 std z+3,R23
04C2 .dbline 368
04C2 ; dd_write_7021_reg(&temp.byte[0]);
04C2 8E01 movw R16,R28
04C4 15DE xcall _dd_write_7021_reg
04C6 .dbline 370
04C6 ;
04C6 ; ADC_readback = dd_read_7021_reg(R7_value); //readback ADC value
04C6 2A2D mov R18,R10
04C8 8E01 movw R16,R28
04CA 0C5F subi R16,252 ; offset = 4
04CC 1F4F sbci R17,255
04CE 98DD xcall _dd_read_7021_reg
04D0 .dbline 371
04D0 ; }
04D0 L59:
04D0 .dbline 373
04D0 ;
04D0 ; dd_set_ADF7021_Power_off();
04D0 4ADE xcall _dd_set_ADF7021_Power_off
04D2 .dbline 376
04D2 ;
04D2 ;
04D2 ; dd_uart_port_tx(&ADC_readback.byte[2], 2);
04D2 22E0 ldi R18,2
04D4 8E01 movw R16,R28
04D6 0A5F subi R16,250 ; offset = 6
04D8 1F4F sbci R17,255
04DA 0E940000 xcall _dd_uart_port_tx
04DE .dbline -2
04DE .dbline 378
04DE ;
04DE ; }
04DE L54:
04DE 2896 adiw R28,8
04E0 0E940000 xcall pop_gset3
04E4 .dbline 0 ; func end
04E4 0895 ret
04E6 .dbsym l ADC_readback 4 S[ADF70XX_REG_T]
04E6 .dbsym l temp 0 S[ADF70XX_REG_T]
04E6 .dbsym r R7_value 10 c
04E6 .dbend
04E6 .dbfunc e test_mode _test_mode fV
04E6 ; test_value -> y+4
04E6 ; register_value -> y+0
.even
04E6 _test_mode::
04E6 0E940000 xcall push_gset2
04EA 2897 sbiw R28,8
04EC .dbline -1
04EC .dbline 382
04EC ; #endif
04EC ;
04EC ; void test_mode(void)
04EC ; {
04EC .dbline 386
04EC ; union ADF70XX_REG_T test_value,register_value;
04EC ;
04EC ; // for ADF7021DB2 864M
04EC ; register_value.whole_reg = 0x000001CC; //for sync word detect;
04EC 4CEC ldi R20,204
04EE 51E0 ldi R21,1
04F0 60E0 ldi R22,0
04F2 70E0 ldi R23,0
04F4 FE01 movw R30,R28
04F6 4083 std z+0,R20
04F8 5183 std z+1,R21
04FA 6283 std z+2,R22
04FC 7383 std z+3,R23
04FE .dbline 387
04FE ; dd_write_7021_reg(®ister_value.byte[0]);
04FE 8E01 movw R16,R28
0500 F7DD xcall _dd_write_7021_reg
0502 .dbline -2
0502 .dbline 432
0502 ; #if 0
0502 ; //write R1, turn on VCO
0502 ; register_value.whole_reg = 0x80535011;
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ;
0502 ; //write R3, turn on TX/RX clocks
0502 ; register_value.whole_reg = 0x2B1734E3;
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ;
0502 ; //write R6 here, if fine IF filter cal is wanted
0502 ;
0502 ;
0502 ; //write R5 to start IF filter cal
0502 ; register_value.whole_reg = 0x00003155; //write R5 to start IF filter cal
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ; dd_short_delay(5); //delay 0.2ms
0502 ;
0502 ; //write R11, configure sync word detect
0502 ; register_value.whole_reg = 0x091A2B3B; //sync word = 0x123456;
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ;
0502 ; //write R12, start sync word detect
0502 ; register_value.whole_reg = 0x000001CC; //for sync word detect;
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ;
0502 ; //write R0, turn on PLL
0502 ; register_value.whole_reg = 0x885d7ef0;
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ; dd_short_delay(0); //delay 40us
0502 ;
0502 ; //write R4, turn on demodulation
0502 ; register_value.whole_reg = 0x80139A14;
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ;
0502 ; if (is_ADF7021_AFC_ON == TRUE)
0502 ; {
0502 ; //write R10, turn AFC on
0502 ; register_value.whole_reg = 0x3296355A;
0502 ; dd_write_7021_reg(®ister_value.byte[0]);
0502 ; }
0502 ;
0502 ; has_set_rx_mode_before = TRUE;
0502 ; phy_state = PHY_IN_RX_MODE;
0502 ; #endif
0502 ; }
0502 L62:
0502 2896 adiw R28,8
0504 0E940000 xcall pop_gset2
0508 .dbline 0 ; func end
0508 0895 ret
050A .dbsym l test_value 4 S[ADF70XX_REG_T]
050A .dbsym l register_value 0 S[ADF70XX_REG_T]
050A .dbend
.area bss(ram, con, rel)
0000 .dbfile D:\icc\examples.avr\230M\dd_adf7021.c
0000 _ADF7021_CE_SIGNAL::
0000 .blkb 1
0001 .dbsym e ADF7021_CE_SIGNAL _ADF7021_CE_SIGNAL c
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