dd_adf7021.lis

ADI公司射频芯片7020＋ATMEGA16射频模块源程序

 026A           ; 
 026A           ; }
 026A           L39:
 026A 2496              adiw R28,4
 026C 0E940000          xcall pop_gset2
 0270                   .dbline 0 ; func end
 0270 0895              ret
 0272                   .dbsym l register_value 0 S[ADF70XX_REG_T]
 0272                   .dbend
 0272                   .dbfunc e dd_set_RX_mode _dd_set_RX_mode fV
 0272           ; register_value -> y+0
                        .even
 0272           _dd_set_RX_mode::
 0272 0E940000          xcall push_gset2
 0276 2497              sbiw R28,4
 0278                   .dbline -1
 0278                   .dbline 216
 0278           ; void dd_set_RX_mode()
 0278           ; {
 0278                   .dbline 222
 0278           ;       union ADF70XX_REG_T register_value;
 0278           ; 
 0278           ;       //      for ADF7021DB2 864M
 0278           ; 
 0278           ;       //write R1, turn on VCO
 0278           ;       register_value.whole_reg = 0x00535011;
 0278 41E1              ldi R20,17
 027A 50E5              ldi R21,80
 027C 63E5              ldi R22,83
 027E 70E0              ldi R23,0
 0280 FE01              movw R30,R28
 0282 4083              std z+0,R20
 0284 5183              std z+1,R21
 0286 6283              std z+2,R22
 0288 7383              std z+3,R23
 028A                   .dbline 223
 028A           ;       dd_write_7021_reg(&register_value.byte[0]);
 028A 8E01              movw R16,R28
 028C 31DF              xcall _dd_write_7021_reg
 028E                   .dbline 226
 028E           ; 
 028E           ;       //write R3, turn on TX/RX clocks
 028E           ;       register_value.whole_reg = 0x2B1734E3;
 028E 43EE              ldi R20,227
 0290 54E3              ldi R21,52
 0292 67E1              ldi R22,23
 0294 7BE2              ldi R23,43
 0296 FE01              movw R30,R28
 0298 4083              std z+0,R20
 029A 5183              std z+1,R21
 029C 6283              std z+2,R22
 029E 7383              std z+3,R23
 02A0                   .dbline 227
 02A0           ;       dd_write_7021_reg(&register_value.byte[0]);
 02A0 8E01              movw R16,R28
 02A2 26DF              xcall _dd_write_7021_reg
 02A4                   .dbline 233
 02A4           ; 
 02A4           ;       //write R6 here, if fine IF filter cal is wanted
 02A4           ; 
 02A4           ; 
 02A4           ;       //write R5 to start IF filter cal
 02A4           ;       register_value.whole_reg = 0x00003155;  //write R5 to start IF filter cal
 02A4 45E5              ldi R20,85
 02A6 51E3              ldi R21,49
 02A8 60E0              ldi R22,0
 02AA 70E0              ldi R23,0
 02AC FE01              movw R30,R28
 02AE 4083              std z+0,R20
 02B0 5183              std z+1,R21
 02B2 6283              std z+2,R22
 02B4 7383              std z+3,R23
 02B6                   .dbline 234
 02B6           ;       dd_write_7021_reg(&register_value.byte[0]);
 02B6 8E01              movw R16,R28
 02B8 1BDF              xcall _dd_write_7021_reg
 02BA                   .dbline 235
 02BA           ;       dd_short_delay(5);              //delay 0.2ms
 02BA 05E0              ldi R16,5
 02BC 0E940000          xcall _dd_short_delay
 02C0                   .dbline 238
 02C0           ; 
 02C0           ;       //write R11, configure sync word detect
 02C0           ;       register_value.whole_reg = 0x091A2B3B;  //sync word = 0x123456;
 02C0 4BE3              ldi R20,59
 02C2 5BE2              ldi R21,43
 02C4 6AE1              ldi R22,26
 02C6 79E0              ldi R23,9
 02C8 FE01              movw R30,R28
 02CA 4083              std z+0,R20
 02CC 5183              std z+1,R21
 02CE 6283              std z+2,R22
 02D0 7383              std z+3,R23
 02D2                   .dbline 239
 02D2           ;       dd_write_7021_reg(&register_value.byte[0]);
 02D2 8E01              movw R16,R28
 02D4 0DDF              xcall _dd_write_7021_reg
 02D6                   .dbline 242
 02D6           ; 
 02D6           ;       //write R12, start sync word detect
 02D6           ;       register_value.whole_reg = 0x0000018C;  //for sync word detect;
 02D6 4CE8              ldi R20,140
 02D8 51E0              ldi R21,1
 02DA 60E0              ldi R22,0
 02DC 70E0              ldi R23,0
 02DE FE01              movw R30,R28
 02E0 4083              std z+0,R20
 02E2 5183              std z+1,R21
 02E4 6283              std z+2,R22
 02E6 7383              std z+3,R23
 02E8                   .dbline 243
 02E8           ;       dd_write_7021_reg(&register_value.byte[0]);
 02E8 8E01              movw R16,R28
 02EA 02DF              xcall _dd_write_7021_reg
 02EC                   .dbline 246
 02EC           ; 
 02EC           ;       //write R0, turn on PLL
 02EC           ;       register_value.whole_reg = 0x095F2DC0;
 02EC 40EC              ldi R20,192
 02EE 5DE2              ldi R21,45
 02F0 6FE5              ldi R22,95
 02F2 79E0              ldi R23,9
 02F4 FE01              movw R30,R28
 02F6 4083              std z+0,R20
 02F8 5183              std z+1,R21
 02FA 6283              std z+2,R22
 02FC 7383              std z+3,R23
 02FE                   .dbline 247
 02FE           ;       dd_write_7021_reg(&register_value.byte[0]);
 02FE 8E01              movw R16,R28
 0300 F7DE              xcall _dd_write_7021_reg
 0302                   .dbline 248
 0302           ;       dd_short_delay(0);              //delay 40us
 0302 0027              clr R16
 0304 0E940000          xcall _dd_short_delay
 0308                   .dbline 251
 0308           ; 
 0308           ;       //write R4, turn on demodulation
 0308           ;       register_value.whole_reg = 0x8016AA14;
 0308 44E1              ldi R20,20
 030A 5AEA              ldi R21,170
 030C 66E1              ldi R22,22
 030E 70E8              ldi R23,128
 0310 FE01              movw R30,R28
 0312 4083              std z+0,R20
 0314 5183              std z+1,R21
 0316 6283              std z+2,R22
 0318 7383              std z+3,R23
 031A                   .dbline 252
 031A           ;       dd_write_7021_reg(&register_value.byte[0]);
 031A 8E01              movw R16,R28
 031C E9DE              xcall _dd_write_7021_reg
 031E                   .dbline 254
 031E           ; 
 031E           ;       if (is_ADF7021_AFC_ON == TRUE)
 031E 80910000          lds R24,_is_ADF7021_AFC_ON
 0322 8130              cpi R24,1
 0324 59F4              brne L43
 0326                   .dbline 255
 0326           ;       {
 0326                   .dbline 257
 0326           ;               //write R10, turn AFC on
 0326           ;               register_value.whole_reg = 0x3296355A;
 0326 4AE5              ldi R20,90
 0328 55E3              ldi R21,53
 032A 66E9              ldi R22,150
 032C 72E3              ldi R23,50
 032E FE01              movw R30,R28
 0330 4083              std z+0,R20
 0332 5183              std z+1,R21
 0334 6283              std z+2,R22
 0336 7383              std z+3,R23
 0338                   .dbline 258
 0338           ;               dd_write_7021_reg(&register_value.byte[0]);
 0338 8E01              movw R16,R28
 033A DADE              xcall _dd_write_7021_reg
 033C                   .dbline 259
 033C           ;       }
 033C           L43:
 033C                   .dbline 261
 033C           ; 
 033C           ;       has_set_rx_mode_before = TRUE;
 033C 81E0              ldi R24,1
 033E 80930000          sts _has_set_rx_mode_before,R24
 0342                   .dbline 262
 0342           ;       phy_state = PHY_IN_RX_MODE;
 0342 83E0              ldi R24,3
 0344 80930000          sts _phy_state,R24
 0348                   .dbline -2
 0348                   .dbline 264
 0348           ; 
 0348           ; }
 0348           L42:
 0348 2496              adiw R28,4
 034A 0E940000          xcall pop_gset2
 034E                   .dbline 0 ; func end
 034E 0895              ret
 0350                   .dbsym l register_value 0 S[ADF70XX_REG_T]
 0350                   .dbend
 0350                   .dbfunc e dd_set_RX_to_TX_mode _dd_set_RX_to_TX_mode fV
 0350           ; register_value -> y+0
                        .even
 0350           _dd_set_RX_to_TX_mode::
 0350 0E940000          xcall push_gset2
 0354 2497              sbiw R28,4
 0356                   .dbline -1
 0356                   .dbline 268
 0356           ; 
 0356           ; 
 0356           ; void dd_set_RX_to_TX_mode()
 0356           ; {
 0356                   .dbline 272
 0356           ;       union ADF70XX_REG_T register_value;
 0356           ; 
 0356           ;       //write R0, switch RX to TX and change LO
 0356           ;       register_value.whole_reg = 0x805d7ef0;
 0356 40EF              ldi R20,240
 0358 5EE7              ldi R21,126
 035A 6DE5              ldi R22,93
 035C 70E8              ldi R23,128
 035E FE01              movw R30,R28
 0360 4083              std z+0,R20
 0362 5183              std z+1,R21
 0364 6283              std z+2,R22
 0366 7383              std z+3,R23
 0368                   .dbline 273
 0368           ;       dd_write_7021_reg(&register_value.byte[0]);
 0368 8E01              movw R16,R28
 036A C2DE              xcall _dd_write_7021_reg
 036C                   .dbline 274
 036C           ;       dd_short_delay(0);              //delay 40us
 036C 0027              clr R16
 036E 0E940000          xcall _dd_short_delay
 0372                   .dbline 278
 0372           ; 
 0372           ;       //please confirm PA level configuration in dd_set_RX_mode(); if it is different, please re-write R2
 0372           ; 
 0372           ;       phy_state = PHY_IN_TX_MODE;
 0372 84E0              ldi R24,4
 0374 80930000          sts _phy_state,R24
 0378                   .dbline -2
 0378                   .dbline 279
 0378           ; }
 0378           L45:
 0378 2496              adiw R28,4
 037A 0E940000          xcall pop_gset2
 037E                   .dbline 0 ; func end
 037E 0895              ret
 0380                   .dbsym l register_value 0 S[ADF70XX_REG_T]
 0380                   .dbend
 0380                   .dbfunc e dd_read_AFC _dd_read_AFC fV
 0380           ;        uartlog -> y+0
                        .even
 0380           _dd_read_AFC::
 0380 2497              sbiw R28,4
 0382                   .dbline -1
 0382                   .dbline 286
 0382           ; 
 0382           ; /****************************************************************************
 0382           ;  *                               readback functions                           *
 0382           ;  ***************************************************************************/
 0382           ; #if 1
 0382           ; void dd_read_AFC(void)
 0382           ; {
 0382                   .dbline 288
 0382           ;       union ADF70XX_REG_T uartlog;
 0382           ;       uartlog = dd_read_7021_reg(0x10);
 0382 20E1              ldi R18,16
 0384 8E01              movw R16,R28
 0386 3CDE              xcall _dd_read_7021_reg
 0388                   .dbline 289
 0388           ;       dd_uart_port_tx(&uartlog.byte[2], 2);
 0388 22E0              ldi R18,2
 038A 8E01              movw R16,R28
 038C 0E5F              subi R16,254  ; offset = 2
 038E 1F4F              sbci R17,255
 0390 0E940000          xcall _dd_uart_port_tx
 0394                   .dbline -2
 0394                   .dbline 290
 0394           ; }
 0394           L46:
 0394 2496              adiw R28,4
 0396                   .dbline 0 ; func end
 0396 0895              ret
 0398                   .dbsym l uartlog 0 S[ADF70XX_REG_T]
 0398                   .dbend
 0398                   .dbfunc e dd_read_RSSI _dd_read_RSSI fV
 0398           ;     RSSI_value -> y+2
 0398           ;           rssi -> y+0
                        .even
 0398           _dd_read_RSSI::
 0398 2697              sbiw R28,6
 039A                   .dbline -1
 039A                   .dbline 297
 039A           ; 
 039A           ; 
 039A           ; 
 039A           ; 
 039A           ; 
 039A           ; void dd_read_RSSI(void)
 039A           ; {
 039A                   .dbline 298
 039A           ;     signed int rssi = 0;
 039A 2224              clr R2
 039C 3324              clr R3
 039E 3982              std y+1,R3
 03A0 2882              std y+0,R2
 03A2                   .dbline 301
 03A2           ;       union ADF70XX_REG_T RSSI_value;
 03A2           ; 
 03A2           ;       RSSI_value = dd_read_7021_reg(0x14);
 03A2 24E1              ldi R18,20
 03A4 8E01              movw R16,R28
 03A6 0E5F              subi R16,254  ; offset = 2
 03A8 1F4F              sbci R17,255
 03AA 2ADE              xcall _dd_read_7021_reg
 03AC                   .dbline 303
 03AC           ; 
 03AC           ;       RSSI_value.whole_reg += RSSI_value.whole_reg ;
 03AC FE01              movw R30,R28
 03AE 2280              ldd R2,z+2
 03B0 3380              ldd R3,z+3
 03B2 4480              ldd R4,z+4
 03B4 5580              ldd R5,z+5
 03B6 FE01              movw R30,R28
 03B8 6280              ldd R6,z+2
 03BA 7380              ldd R7,z+3
 03BC 8480              ldd R8,z+4
 03BE 9580              ldd R9,z+5
 03C0 620C              add R6,R2
 03C2 731C              adc R7,R3
 03C4 841C              adc R8,R4
 03C6 951C              adc R9,R5
 03C8 FE01              movw R30,R28
 03CA 6282              std z+2,R6
 03CC 7382              std z+3,R7
 03CE 8482              std z+4,R8
 03D0 9582              std z+5,R9
 03D2                   .dbline 305
 03D2           ; 
 03D2           ;     rssi = RSSI_value.byte[3];
 03D2 2D80              ldd R2,y+5
 03D4 3324              clr R3
 03D6 3982              std y+1,R3
 03D8 2882              std y+0,R2
 03DA                   .dbline 306
 03DA           ;       rssi += gain_correction[RSSI_value.byte[2] & 0x0F] ;
 03DA 80E0              ldi R24,<_gain_correction
 03DC 90E0              ldi R25,>_gain_correction
 03DE EC81              ldd R30,y+4
 03E0 FF27              clr R31
 03E2 EF70              andi R30,15
 03E4 F070              andi R31,0
 03E6 E80F              add R30,R24
 03E8 F91F              adc R31,R25
 03EA 2490              lpm R2,Z
 03EC 3324              clr R3