📄 dd_adf7021.lis
字号:
0118 .dbline 116
0118 ; {PORTA |= 1<<ADF7021_SDATA;}
0118 .dbline 116
0118 DA9A sbi 0x1b,2
011A .dbline 116
011A 01C0 xjmp L29
011C L28:
011C .dbline 118
011C ; else
011C ; {PORTA &= ~(1<<ADF7021_SDATA);}
011C .dbline 118
011C DA98 cbi 0x1b,2
011E .dbline 118
011E L29:
011E .dbline 121
011E D89A sbi 0x1b,0
0120 .dbline 122
0120 AA0C add R10,R10
0122 .dbline 123
0122 L25:
0122 .dbline 112
0122 6A95 dec R22
0124 L27:
0124 .dbline 112
0124 2224 clr R2
0126 2616 cp R2,R22
0128 94F3 brlt L24
012A .dbline 124
012A D898 cbi 0x1b,0
012C .dbline 125
012C L21:
012C .dbline 107
012C 4A95 dec R20
012E L23:
012E .dbline 107
012E 4030 cpi R20,0
0130 2CF7 brge L20
0132 .dbline 130
0132 ;
0132 ;
0132 ; PORTA |= 1<<ADF7021_SCLK;
0132 ; byte += byte; // left shift 1
0132 ; }
0132 ; PORTA &= ~(1<<ADF7021_SCLK);
0132 ; }
0132 ;
0132 ;
0132 ; /* Strobe the latch */
0132 ;
0132 ; PORTA |= 1<<ADF7021_SLE;
0132 DB9A sbi 0x1b,3
0134 .dbline 131
0134 ; PORTA |= 1<<ADF7021_SLE; // Slight pulse extend
0134 DB9A sbi 0x1b,3
0136 .dbline 132
0136 ; PORTA &= ~(1<<ADF7021_SDATA);
0136 DA98 cbi 0x1b,2
0138 .dbline 133
0138 ; PORTA &= ~(1<<ADF7021_SLE);
0138 DB98 cbi 0x1b,3
013A .dbline -2
013A .dbline 137
013A ;
013A ; /* All port lines left low */
013A ;
013A ; }
013A L19:
013A 0E940000 xcall pop_gset3
013E .dbline 0 ; func end
013E 0895 ret
0140 .dbsym r i 20 C
0140 .dbsym r j 22 C
0140 .dbsym r byte 10 c
0140 .dbsym r reg_bytes 16 pc
0140 .dbend
0140 .dbfunc e dd_set_ADF7021_Power_on _dd_set_ADF7021_Power_on fV
.even
0140 _dd_set_ADF7021_Power_on::
0140 .dbline -1
0140 .dbline 141
0140 ;
0140 ;
0140 ; void dd_set_ADF7021_Power_on(void)
0140 ; {
0140 .dbline 142
0140 ; if (ADF7021_CE_SIGNAL == 0)
0140 20900000 lds R2,_ADF7021_CE_SIGNAL
0144 2220 tst R2
0146 71F4 brne L31
0148 .dbline 143
0148 ; {
0148 .dbline 144
0148 ; PORTB |= 1<<ADF7021_CE;
0148 C39A sbi 0x18,3
014A .dbline 145
014A ; ADF7021_CE_SIGNAL=1;
014A 81E0 ldi R24,1
014C 80930000 sts _ADF7021_CE_SIGNAL,R24
0150 .dbline 146
0150 ; phy_state = PHY_POWERON;
0150 82E0 ldi R24,2
0152 80930000 sts _phy_state,R24
0156 .dbline 147
0156 ; if ( is_use_crystal == TRUE ) dd_short_delay(25); //delay 1ms
0156 80910000 lds R24,_is_use_crystal
015A 8130 cpi R24,1
015C 19F4 brne L33
015E .dbline 147
015E 09E1 ldi R16,25
0160 0E940000 xcall _dd_short_delay
0164 L33:
0164 .dbline 148
0164 L31:
0164 .dbline -2
0164 .dbline 149
0164 ; }
0164 ; }
0164 L30:
0164 .dbline 0 ; func end
0164 0895 ret
0166 .dbend
0166 .dbfunc e dd_set_ADF7021_Power_off _dd_set_ADF7021_Power_off fV
0166 ; register_value -> y+0
.even
0166 _dd_set_ADF7021_Power_off::
0166 0E940000 xcall push_gset2
016A 2497 sbiw R28,4
016C .dbline -1
016C .dbline 153
016C ;
016C ;
016C ; void dd_set_ADF7021_Power_off(void)
016C ; {
016C .dbline 157
016C ; union ADF70XX_REG_T register_value;
016C ;
016C ;
016C ; if ((ADF7021_CE_SIGNAL == 1) && (is_internal_PA_ramp_used == TRUE))
016C 80910000 lds R24,_ADF7021_CE_SIGNAL
0170 8130 cpi R24,1
0172 91F4 brne L36
0174 80910000 lds R24,_is_internal_PA_ramp_used
0178 8130 cpi R24,1
017A 71F4 brne L36
017C .dbline 158
017C ; {
017C .dbline 159
017C ; register_value.whole_reg = 0x00685502; //Ramp Rate = 16 codes/bit, close PA firstly
017C 42E0 ldi R20,2
017E 55E5 ldi R21,85
0180 68E6 ldi R22,104
0182 70E0 ldi R23,0
0184 FE01 movw R30,R28
0186 4083 std z+0,R20
0188 5183 std z+1,R21
018A 6283 std z+2,R22
018C 7383 std z+3,R23
018E .dbline 160
018E ; dd_write_7021_reg(®ister_value.byte[0]);
018E 8E01 movw R16,R28
0190 AFDF xcall _dd_write_7021_reg
0192 .dbline 161
0192 ; dd_short_delay(100); //delay for 4 bits
0192 04E6 ldi R16,100
0194 0E940000 xcall _dd_short_delay
0198 .dbline 162
0198 ; }
0198 L36:
0198 .dbline 163
0198 ; ADF7021_CE_SIGNAL = 0;
0198 2224 clr R2
019A 20920000 sts _ADF7021_CE_SIGNAL,R2
019E .dbline 164
019E ; PORTB &= ~(1<<ADF7021_CE);
019E C398 cbi 0x18,3
01A0 .dbline 166
01A0 ;
01A0 ; has_set_tx_mode_before = FALSE;
01A0 20920000 sts _has_set_tx_mode_before,R2
01A4 .dbline 167
01A4 ; has_set_rx_mode_before = FALSE;
01A4 20920000 sts _has_set_rx_mode_before,R2
01A8 .dbline 169
01A8 ;
01A8 ; phy_state = PHY_DISABLED;
01A8 81E0 ldi R24,1
01AA 80930000 sts _phy_state,R24
01AE .dbline -2
01AE .dbline 170
01AE ; }
01AE L35:
01AE 2496 adiw R28,4
01B0 0E940000 xcall pop_gset2
01B4 .dbline 0 ; func end
01B4 0895 ret
01B6 .dbsym l register_value 0 S[ADF70XX_REG_T]
01B6 .dbend
01B6 .dbfunc e dd_set_TX_to_RX_mode _dd_set_TX_to_RX_mode fV
01B6 ; register_value -> y+0
.even
01B6 _dd_set_TX_to_RX_mode::
01B6 0E940000 xcall push_gset2
01BA 2497 sbiw R28,4
01BC .dbline -1
01BC .dbline 174
01BC ;
01BC ;
01BC ; void dd_set_TX_to_RX_mode(void)
01BC ; {
01BC .dbline 178
01BC ; union ADF70XX_REG_T register_value;
01BC ;
01BC ; //write R0, switch TX to RX and change LO
01BC ; register_value.whole_reg = 0x885d7ef0;
01BC 40EF ldi R20,240
01BE 5EE7 ldi R21,126
01C0 6DE5 ldi R22,93
01C2 78E8 ldi R23,136
01C4 FE01 movw R30,R28
01C6 4083 std z+0,R20
01C8 5183 std z+1,R21
01CA 6283 std z+2,R22
01CC 7383 std z+3,R23
01CE .dbline 179
01CE ; dd_write_7021_reg(®ister_value.byte[0]);
01CE 8E01 movw R16,R28
01D0 8FDF xcall _dd_write_7021_reg
01D2 .dbline 180
01D2 ; dd_short_delay(0); //delay 40us
01D2 0027 clr R16
01D4 0E940000 xcall _dd_short_delay
01D8 .dbline 182
01D8 ;
01D8 ; phy_state = PHY_IN_RX_MODE;
01D8 83E0 ldi R24,3
01DA 80930000 sts _phy_state,R24
01DE .dbline -2
01DE .dbline 183
01DE ; }
01DE L38:
01DE 2496 adiw R28,4
01E0 0E940000 xcall pop_gset2
01E4 .dbline 0 ; func end
01E4 0895 ret
01E6 .dbsym l register_value 0 S[ADF70XX_REG_T]
01E6 .dbend
01E6 .dbfunc e dd_set_TX_mode _dd_set_TX_mode fV
01E6 ; register_value -> y+0
.even
01E6 _dd_set_TX_mode::
01E6 0E940000 xcall push_gset2
01EA 2497 sbiw R28,4
01EC .dbline -1
01EC .dbline 186
01EC ;
01EC ; void dd_set_TX_mode()
01EC ; {
01EC .dbline 192
01EC ; union ADF70XX_REG_T register_value;
01EC ;
01EC ; // for ADF7021DB2 864M
01EC ;
01EC ; //write R1, turn on VCO
01EC ; register_value.whole_reg = 0x00535011;
01EC 41E1 ldi R20,17
01EE 50E5 ldi R21,80
01F0 63E5 ldi R22,83
01F2 70E0 ldi R23,0
01F4 FE01 movw R30,R28
01F6 4083 std z+0,R20
01F8 5183 std z+1,R21
01FA 6283 std z+2,R22
01FC 7383 std z+3,R23
01FE .dbline 193
01FE ; dd_write_7021_reg(®ister_value.byte[0]);
01FE 8E01 movw R16,R28
0200 77DF xcall _dd_write_7021_reg
0202 .dbline 194
0202 ; dd_short_delay(20); //delay 800us
0202 04E1 ldi R16,20
0204 0E940000 xcall _dd_short_delay
0208 .dbline 197
0208 ;
0208 ; //write R3, turn on TX/RX clocks
0208 ; register_value.whole_reg = 0x2B1734E3;
0208 43EE ldi R20,227
020A 54E3 ldi R21,52
020C 67E1 ldi R22,23
020E 7BE2 ldi R23,43
0210 FE01 movw R30,R28
0212 4083 std z+0,R20
0214 5183 std z+1,R21
0216 6283 std z+2,R22
0218 7383 std z+3,R23
021A .dbline 198
021A ; dd_write_7021_reg(®ister_value.byte[0]);
021A 8E01 movw R16,R28
021C 69DF xcall _dd_write_7021_reg
021E .dbline 201
021E ;
021E ; //write R0, turn on PLL
021E ; register_value.whole_reg = 0x015F3820;
021E 40E2 ldi R20,32
0220 58E3 ldi R21,56
0222 6FE5 ldi R22,95
0224 71E0 ldi R23,1
0226 FE01 movw R30,R28
0228 4083 std z+0,R20
022A 5183 std z+1,R21
022C 6283 std z+2,R22
022E 7383 std z+3,R23
0230 .dbline 202
0230 ; dd_write_7021_reg(®ister_value.byte[0]);
0230 8E01 movw R16,R28
0232 5EDF xcall _dd_write_7021_reg
0234 .dbline 203
0234 ; dd_short_delay(0); //delay 40us
0234 0027 clr R16
0236 0E940000 xcall _dd_short_delay
023A .dbline 206
023A ;
023A ; //write R2, turn on PA
023A ; register_value.whole_reg = 0x00685582; //Ramp Rate = 16 codes/bit, TX level = 2;
023A 42E8 ldi R20,130
023C 55E5 ldi R21,85
023E 68E6 ldi R22,104
0240 70E0 ldi R23,0
0242 FE01 movw R30,R28
0244 4083 std z+0,R20
0246 5183 std z+1,R21
0248 6283 std z+2,R22
024A 7383 std z+3,R23
024C .dbline 208
024C ; // register_value.whole_reg = 0x006FF582; //max power TX
024C ; dd_write_7021_reg(®ister_value.byte[0]);
024C 8E01 movw R16,R28
024E 50DF xcall _dd_write_7021_reg
0250 .dbline 209
0250 ; if (is_internal_PA_ramp_used == TRUE) dd_short_delay(100); //delay for 4ms, 4 bits for DR = 1Kbps
0250 80910000 lds R24,_is_internal_PA_ramp_used
0254 8130 cpi R24,1
0256 19F4 brne L40
0258 .dbline 209
0258 04E6 ldi R16,100
025A 0E940000 xcall _dd_short_delay
025E L40:
025E .dbline 211
025E ;
025E ; has_set_tx_mode_before = TRUE;
025E 81E0 ldi R24,1
0260 80930000 sts _has_set_tx_mode_before,R24
0264 .dbline 212
0264 ; phy_state = PHY_IN_TX_MODE;
0264 84E0 ldi R24,4
0266 80930000 sts _phy_state,R24
026A .dbline -2
026A .dbline 214
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