📄 dd_adf7021.lis
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.module dd_adf7021.c
.area vector(rom, abs)
.org 40
0028 0C940000 jmp _dd_spi_i2c_isr
.org 72
0048 0C940000 jmp _dd_adf7021_sync_isr
.org 44
002C 0C940000 jmp _UART_RECV_DEAL
.org 52
0034 0C940000 jmp _UART_SEND_DEAL
.area code(ram, con, rel)
.area lit(rom, con, rel)
0000 _gain_correction::
0000 AC00 .byte 172,0
0002 0000 .byte 0,0
0004 744C .byte 't,'L
0006 3000 .byte 48,0
0008 0000 .byte 0,0
000A 0000 .byte 0,0
000C 0000 .byte 0,0
000E 0000 .byte 0,0
0010 .dbfile D:\icc\examples.avr\230M\dd_adf7021.c
0010 .dbsym e gain_correction _gain_correction A[16:16]kc
.area code(ram, con, rel)
0000 .dbfile D:\icc\examples.avr\230M\dd_adf7021.c
.area text(rom, con, rel)
0000 .dbfile D:\icc\examples.avr\230M\dd_adf7021.c
0000 .dbunion 0 4 ADF70XX_REG_T
0000 .dbfield 0 whole_reg l
0000 .dbfield 0 byte A[4:4]c
0000 .dbend
0000 .dbfunc e dd_read_7021_reg _dd_read_7021_reg fS[ADF70XX_REG_T]
0000 ; register_value -> y+0
0000 ; i -> R10
0000 ; j -> R12
0000 ; byte -> R14
0000 ; readback_config -> R10
.even
0000 _dd_read_7021_reg::
0000 0E940000 xcall push_arg4
0004 0E940000 xcall push_gset5
0008 A22E mov R10,R18
000A 2497 sbiw R28,4
000C .dbline -1
000C .dbline 34
000C ; #include "dd.h"
000C ; //#include "api.h"
000C ;
000C ; #if 0
000C ; union ADF70XX_REG_T
000C ; {
000C ; unsigned long whole_reg;
000C ; unsigned char byte[4]; // Warning: Be endian-specific when accessing bytes
000C ;
000C ; };
000C ;
000C ; struct MAC_PACKET_HEADER_T
000C ; {
000C ; unsigned int seq_number;
000C ; unsigned char short_address;
000C ; unsigned char payload_length;
000C ;
000C ; };
000C ; #endif
000C ; unsigned char ADF7021_CE_SIGNAL;
000C ; #pragma data:code
000C ; const unsigned char gain_correction[] =
000C ; { 2*86, 0, 0, 0, 2*58, 2*38, 2*24, 0,
000C ; 0, 0, 0, 0, 0, 0, 0, 0 }; // 7021
000C ; #pragma data:code
000C ;
000C ; /****************************************************************************
000C ; * ADF7021 Control Functions *
000C ; ****************************************************************************/
000C ;
000C ;
000C ;
000C ; union ADF70XX_REG_T dd_read_7021_reg(unsigned char readback_config)
000C ; {
000C .dbline 42
000C ; union ADF70XX_REG_T register_value;
000C ; unsigned char i, j;
000C ; unsigned char byte;
000C ;
000C ;
000C ; #if 1
000C ; /* Write readback and ADC control value */
000C ; register_value.whole_reg = ((readback_config & 0x1F) << 4);
000C 8A2D mov R24,R10
000E 9927 clr R25
0010 8F71 andi R24,31
0012 9070 andi R25,0
0014 880F lsl R24
0016 991F rol R25
0018 880F lsl R24
001A 991F rol R25
001C 880F lsl R24
001E 991F rol R25
0020 880F lsl R24
0022 991F rol R25
0024 1C01 movw R2,R24
0026 4424 clr R4
0028 37FC sbrc R3,7
002A 4094 com R4
002C 5524 clr R5
002E 47FC sbrc R4,7
0030 5094 com R5
0032 FE01 movw R30,R28
0034 2082 std z+0,R2
0036 3182 std z+1,R3
0038 4282 std z+2,R4
003A 5382 std z+3,R5
003C .dbline 43
003C ; register_value.whole_reg |= 7; // Address the readback setup register
003C 47E0 ldi R20,7
003E 50E0 ldi R21,0
0040 60E0 ldi R22,0
0042 70E0 ldi R23,0
0044 FE01 movw R30,R28
0046 2080 ldd R2,z+0
0048 3180 ldd R3,z+1
004A 4280 ldd R4,z+2
004C 5380 ldd R5,z+3
004E 242A or R2,R20
0050 352A or R3,R21
0052 462A or R4,R22
0054 572A or R5,R23
0056 FE01 movw R30,R28
0058 2082 std z+0,R2
005A 3182 std z+1,R3
005C 4282 std z+2,R4
005E 5382 std z+3,R5
0060 .dbline 45
0060 ;
0060 ; dd_write_7021_reg((unsigned char *)®ister_value);
0060 8E01 movw R16,R28
0062 46D0 xcall _dd_write_7021_reg
0064 .dbline 47
0064 ;
0064 ; register_value.whole_reg = 0;
0064 40E0 ldi R20,0
0066 50E0 ldi R21,0
0068 60E0 ldi R22,0
006A 70E0 ldi R23,0
006C FE01 movw R30,R28
006E 4083 std z+0,R20
0070 5183 std z+1,R21
0072 6283 std z+2,R22
0074 7383 std z+3,R23
0076 .dbline 52
0076 ; #endif
0076 ;
0076 ; /* Read back value */
0076 ;
0076 ; PORTA &= ~(1<<ADF7021_SDATA);
0076 DA98 cbi 0x1b,2
0078 .dbline 53
0078 ; PORTA &= ~(1<<ADF7021_SCLK);
0078 D898 cbi 0x1b,0
007A .dbline 54
007A ; PORTA |= 1<<ADF7021_SLE;
007A DB9A sbi 0x1b,3
007C .dbline 57
007C ;
007C ; //Clock in first bit and discard
007C ; PORTA |= 1<<ADF7021_SCLK;
007C D89A sbi 0x1b,0
007E .dbline 58
007E ; byte = 0; // Slight pulse extend
007E EE24 clr R14
0080 .dbline 59
0080 ; PORTA &= ~(1<<ADF7021_SCLK);
0080 D898 cbi 0x1b,0
0082 .dbline 63
0082 ;
0082 ;
0082 ; /* Clock in data MSbit first */
0082 ; for (i=2; i<=3; i++)
0082 82E0 ldi R24,2
0084 A82E mov R10,R24
0086 1EC0 xjmp L12
0088 L9:
0088 .dbline 64
0088 ; {
0088 .dbline 65
0088 ; for (j=8; j>0; j--)
0088 88E0 ldi R24,8
008A C82E mov R12,R24
008C 0BC0 xjmp L16
008E L13:
008E .dbline 66
008E ; {
008E .dbline 67
008E ; PORTA |= 1<<ADF7021_SCLK;
008E D89A sbi 0x1b,0
0090 .dbline 68
0090 ; byte += byte; // left shift 1
0090 EE0C add R14,R14
0092 .dbline 69
0092 ; PORTA &= ~(1<<ADF7021_SCLK);
0092 D898 cbi 0x1b,0
0094 .dbline 71
0094 ;
0094 ; if ((PINA&0x02)==0x02) byte |= 1;
0094 89B3 in R24,0x19
0096 8270 andi R24,2
0098 8230 cpi R24,2
009A 19F4 brne L17
009C .dbline 71
009C 8E2D mov R24,R14
009E 8160 ori R24,1
00A0 E82E mov R14,R24
00A2 L17:
00A2 .dbline 72
00A2 L14:
00A2 .dbline 65
00A2 CA94 dec R12
00A4 L16:
00A4 .dbline 65
00A4 2224 clr R2
00A6 2C14 cp R2,R12
00A8 90F3 brlo L13
00AA .dbline 74
00AA CE01 movw R24,R28
00AC EA2D mov R30,R10
00AE FF27 clr R31
00B0 E80F add R30,R24
00B2 F91F adc R31,R25
00B4 E082 std z+0,R14
00B6 .dbline 76
00B6 01E0 ldi R16,1
00B8 10E0 ldi R17,0
00BA 20E0 ldi R18,0
00BC 30E0 ldi R19,0
00BE 0E940000 xcall _my_delay
00C2 .dbline 78
00C2 L10:
00C2 .dbline 63
00C2 A394 inc R10
00C4 L12:
00C4 .dbline 63
00C4 83E0 ldi R24,3
00C6 8A15 cp R24,R10
00C8 F8F6 brsh L9
00CA .dbline 80
00CA ; }
00CA ;
00CA ; register_value.byte[i] = byte;
00CA ;
00CA ; my_delay(1); //wait for a bit time
00CA ;
00CA ; }//for i=2 : 3;
00CA ;
00CA ; PORTA |= 1<<ADF7021_SCLK;
00CA D89A sbi 0x1b,0
00CC .dbline 81
00CC ; PORTA &= ~(1<<ADF7021_SCLK);
00CC D898 cbi 0x1b,0
00CE .dbline 87
00CE ;
00CE ; /*
00CE ; ADF7021_SCLK = 1;
00CE ; ADF7021_SCLK = 0;
00CE ; */
00CE ; PORTA &= ~(1<<ADF7021_SLE);
00CE DB98 cbi 0x1b,3
00D0 .dbline 90
00D0 ; // All port lines left low
00D0 ;
00D0 ; return register_value;
00D0 CE01 movw R24,R28
00D2 2E84 ldd R2,y+14
00D4 3F84 ldd R3,y+15
00D6 04E0 ldi R16,4
00D8 10E0 ldi R17,0
00DA 3A92 st -y,R3
00DC 2A92 st -y,R2
00DE 9A93 st -y,R25
00E0 8A93 st -y,R24
00E2 0E940000 xcall asgnblk
00E6 .dbline -2
00E6 L7:
00E6 2496 adiw R28,4
00E8 0E940000 xcall pop_gset5
00EC 2496 adiw R28,4
00EE .dbline 0 ; func end
00EE 0895 ret
00F0 .dbsym l register_value 0 S[ADF70XX_REG_T]
00F0 .dbsym r i 10 c
00F0 .dbsym r j 12 c
00F0 .dbsym r byte 14 c
00F0 .dbsym r readback_config 10 c
00F0 .dbend
00F0 .dbfunc e dd_write_7021_reg _dd_write_7021_reg fV
00F0 ; i -> R20
00F0 ; j -> R22
00F0 ; byte -> R10
00F0 ; reg_bytes -> R16,R17
.even
00F0 _dd_write_7021_reg::
00F0 0E940000 xcall push_gset3
00F4 .dbline -1
00F4 .dbline 97
00F4 ; }
00F4 ;
00F4 ;
00F4 ;
00F4 ;
00F4 ; void dd_write_7021_reg(unsigned char * reg_bytes)
00F4 ; {
00F4 .dbline 101
00F4 ; signed char i, j;
00F4 ; unsigned char byte;
00F4 ;
00F4 ; PORTA &= ~(1<<ADF7021_SLE);
00F4 DB98 cbi 0x1b,3
00F6 .dbline 102
00F6 ; PORTA &= ~(1<<ADF7021_SCLK);
00F6 D898 cbi 0x1b,0
00F8 .dbline 107
00F8 ;
00F8 ;
00F8 ; /* Clock data out MSbit first */
00F8 ;
00F8 ; for (i=3; i>=0; i--)
00F8 43E0 ldi R20,3
00FA 19C0 xjmp L23
00FC L20:
00FC .dbline 109
00FC ;
00FC ; {
00FC .dbline 110
00FC ; byte = reg_bytes[i];
00FC E42F mov R30,R20
00FE FF27 clr R31
0100 E7FD sbrc R30,7
0102 F095 com R31
0104 E00F add R30,R16
0106 F11F adc R31,R17
0108 A080 ldd R10,z+0
010A .dbline 112
010A ;
010A ; for (j=8; j>0; j--)
010A 68E0 ldi R22,8
010C 0BC0 xjmp L27
010E L24:
010E .dbline 113
010E ; {
010E .dbline 114
010E ; PORTA &= ~(1<<ADF7021_SCLK);
010E D898 cbi 0x1b,0
0110 .dbline 115
0110 ; if ((byte & 0x80)==0x80)
0110 8A2D mov R24,R10
0112 8078 andi R24,128
0114 8038 cpi R24,128
0116 11F4 brne L28
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