dd_adf7021.s

ADI公司射频芯片7020＋ATMEGA16射频模块源程序

; 
; }
L39:
	adiw R28,4
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym l register_value 0 S[ADF70XX_REG_T]
	.dbend
	.dbfunc e dd_set_RX_mode _dd_set_RX_mode fV
; register_value -> y+0
	.even
_dd_set_RX_mode::
	xcall push_gset2
	sbiw R28,4
	.dbline -1
	.dbline 216
; void dd_set_RX_mode()
; {
	.dbline 222
; 	union ADF70XX_REG_T register_value;
; 
; 	//	for ADF7021DB2 864M
; 
; 	//write R1, turn on VCO
; 	register_value.whole_reg = 0x00535011;
	ldi R20,17
	ldi R21,80
	ldi R22,83
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 223
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 226
; 
; 	//write R3, turn on TX/RX clocks
; 	register_value.whole_reg = 0x2B1734E3;
	ldi R20,227
	ldi R21,52
	ldi R22,23
	ldi R23,43
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 227
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 233
; 
; 	//write R6 here, if fine IF filter cal is wanted
; 
; 
; 	//write R5 to start IF filter cal
; 	register_value.whole_reg = 0x00003155;	//write R5 to start IF filter cal
	ldi R20,85
	ldi R21,49
	ldi R22,0
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 234
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 235
; 	dd_short_delay(5);		//delay 0.2ms
	ldi R16,5
	xcall _dd_short_delay
	.dbline 238
; 
; 	//write R11, configure sync word detect
; 	register_value.whole_reg = 0x091A2B3B;	//sync word = 0x123456;
	ldi R20,59
	ldi R21,43
	ldi R22,26
	ldi R23,9
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 239
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 242
; 
; 	//write R12, start sync word detect
; 	register_value.whole_reg = 0x0000018C;	//for sync word detect;
	ldi R20,140
	ldi R21,1
	ldi R22,0
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 243
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 246
; 
; 	//write R0, turn on PLL
; 	register_value.whole_reg = 0x095F2DC0;
	ldi R20,192
	ldi R21,45
	ldi R22,95
	ldi R23,9
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 247
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 248
; 	dd_short_delay(0);		//delay 40us
	clr R16
	xcall _dd_short_delay
	.dbline 251
; 
; 	//write R4, turn on demodulation
; 	register_value.whole_reg = 0x8016AA14;
	ldi R20,20
	ldi R21,170
	ldi R22,22
	ldi R23,128
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 252
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 254
; 
; 	if (is_ADF7021_AFC_ON == TRUE)
	lds R24,_is_ADF7021_AFC_ON
	cpi R24,1
	brne L43
	.dbline 255
; 	{
	.dbline 257
; 		//write R10, turn AFC on
; 		register_value.whole_reg = 0x3296355A;
	ldi R20,90
	ldi R21,53
	ldi R22,150
	ldi R23,50
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 258
; 		dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 259
; 	}
L43:
	.dbline 261
; 
; 	has_set_rx_mode_before = TRUE;
	ldi R24,1
	sts _has_set_rx_mode_before,R24
	.dbline 262
; 	phy_state = PHY_IN_RX_MODE;
	ldi R24,3
	sts _phy_state,R24
	.dbline -2
	.dbline 264
; 
; }
L42:
	adiw R28,4
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym l register_value 0 S[ADF70XX_REG_T]
	.dbend
	.dbfunc e dd_set_RX_to_TX_mode _dd_set_RX_to_TX_mode fV
; register_value -> y+0
	.even
_dd_set_RX_to_TX_mode::
	xcall push_gset2
	sbiw R28,4
	.dbline -1
	.dbline 268
; 
; 
; void dd_set_RX_to_TX_mode()
; {
	.dbline 272
; 	union ADF70XX_REG_T register_value;
; 
; 	//write R0, switch RX to TX and change LO
; 	register_value.whole_reg = 0x805d7ef0;
	ldi R20,240
	ldi R21,126
	ldi R22,93
	ldi R23,128
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 273
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 274
; 	dd_short_delay(0);		//delay 40us
	clr R16
	xcall _dd_short_delay
	.dbline 278
; 
; 	//please confirm PA level configuration in dd_set_RX_mode(); if it is different, please re-write R2
; 
; 	phy_state = PHY_IN_TX_MODE;
	ldi R24,4
	sts _phy_state,R24
	.dbline -2
	.dbline 279
; }
L45:
	adiw R28,4
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym l register_value 0 S[ADF70XX_REG_T]
	.dbend
	.dbfunc e dd_read_AFC _dd_read_AFC fV
;        uartlog -> y+0
	.even
_dd_read_AFC::
	sbiw R28,4
	.dbline -1
	.dbline 286
; 
; /****************************************************************************
;  *                   		   readback functions                           *
;  ***************************************************************************/
; #if 1
; void dd_read_AFC(void)
; {
	.dbline 288
; 	union ADF70XX_REG_T uartlog;
; 	uartlog = dd_read_7021_reg(0x10);
	ldi R18,16
	movw R16,R28
	xcall _dd_read_7021_reg
	.dbline 289
; 	dd_uart_port_tx(&uartlog.byte[2], 2);
	ldi R18,2
	movw R16,R28
	subi R16,254  ; offset = 2
	sbci R17,255
	xcall _dd_uart_port_tx
	.dbline -2
	.dbline 290
; }
L46:
	adiw R28,4
	.dbline 0 ; func end
	ret
	.dbsym l uartlog 0 S[ADF70XX_REG_T]
	.dbend
	.dbfunc e dd_read_RSSI _dd_read_RSSI fV
;     RSSI_value -> y+2
;           rssi -> y+0
	.even
_dd_read_RSSI::
	sbiw R28,6
	.dbline -1
	.dbline 297
; 
; 
; 
; 
; 
; void dd_read_RSSI(void)
; {
	.dbline 298
;     signed int rssi = 0;
	clr R2
	clr R3
	std y+1,R3
	std y+0,R2
	.dbline 301
; 	union ADF70XX_REG_T RSSI_value;
; 
; 	RSSI_value = dd_read_7021_reg(0x14);
	ldi R18,20
	movw R16,R28
	subi R16,254  ; offset = 2
	sbci R17,255
	xcall _dd_read_7021_reg
	.dbline 303
; 
; 	RSSI_value.whole_reg += RSSI_value.whole_reg ;
	movw R30,R28
	ldd R2,z+2
	ldd R3,z+3
	ldd R4,z+4
	ldd R5,z+5
	movw R30,R28
	ldd R6,z+2
	ldd R7,z+3
	ldd R8,z+4
	ldd R9,z+5
	add R6,R2
	adc R7,R3
	adc R8,R4
	adc R9,R5
	movw R30,R28
	std z+2,R6
	std z+3,R7
	std z+4,R8
	std z+5,R9
	.dbline 305
; 
;     rssi = RSSI_value.byte[3];
	ldd R2,y+5
	clr R3
	std y+1,R3
	std y+0,R2
	.dbline 306
; 	rssi += gain_correction[RSSI_value.byte[2] & 0x0F] ;
	ldi R24,<_gain_correction
	ldi R25,>_gain_correction
	ldd R30,y+4
	clr R31
	andi R30,15
	andi R31,0
	add R30,R24
	adc R31,R25
	lpm R2,Z
	clr R3
	ldd R4,y+0
	ldd R5,y+1
	add R4,R2
	adc R5,R3
	std y+1,R5
	std y+0,R4
	.dbline 307
;     rssi = rssi /4 ;
	ldi R18,4
	ldi R19,0
	movw R16,R4
	xcall div16s
	std y+1,R17
	std y+0,R16
	.dbline 310
; 	//RSSI(dBm) = rssi + 130
; 
; 	dd_uart_port_tx((unsigned char *)&rssi, 2);
	ldi R18,2
	movw R16,R28
	xcall _dd_uart_port_tx
	.dbline -2
	.dbline 311
; }
L48:
	adiw R28,6
	.dbline 0 ; func end
	ret
	.dbsym l RSSI_value 2 S[ADF70XX_REG_T]
	.dbsym l rssi 0 I
	.dbend
	.dbfunc e dd_read_filter_cal _dd_read_filter_cal fV
;        uartlog -> y+0
	.even
_dd_read_filter_cal::
	sbiw R28,4
	.dbline -1
	.dbline 316
; 
; 
; 
; void dd_read_filter_cal(void)
; {
	.dbline 320
; 	union ADF70XX_REG_T uartlog;
; 
; 	//dd_set_ADF7021_Power_on();
; 	uartlog = dd_read_7021_reg(0x18);
	ldi R18,24
	movw R16,R28
	xcall _dd_read_7021_reg
	.dbline 321
; 	dd_uart_port_tx(&uartlog.byte[2], 2);
	ldi R18,2
	movw R16,R28
	subi R16,254  ; offset = 2
	sbci R17,255
	xcall _dd_uart_port_tx
	.dbline -2
	.dbline 322
; }
L51:
	adiw R28,4
	.dbline 0 ; func end
	ret
	.dbsym l uartlog 0 S[ADF70XX_REG_T]
	.dbend
	.dbfunc e dd_read_ADF70XX_version _dd_read_ADF70XX_version fV
;        uartlog -> y+0
	.even
_dd_read_ADF70XX_version::
	sbiw R28,4
	.dbline -1
	.dbline 327
; 
; 
; 
; void dd_read_ADF70XX_version(void)
; {
	.dbline 330
; 	union ADF70XX_REG_T uartlog;
; 
; 	dd_set_ADF7021_Power_on();
	xcall _dd_set_ADF7021_Power_on
	.dbline 331
; 	uartlog = dd_read_7021_reg(0x1C);
	ldi R18,28
	movw R16,R28
	xcall _dd_read_7021_reg
	.dbline -2
	.dbline 333
; 	//dd_uart_port_tx(&uartlog.byte[2], 2);
; }
L53:
	adiw R28,4
	.dbline 0 ; func end
	ret
	.dbsym l uartlog 0 S[ADF70XX_REG_T]
	.dbend
	.dbfunc e dd_ADC_readback _dd_ADC_readback fV
;   ADC_readback -> y+4
;           temp -> y+0
;       R7_value -> R10
	.even
_dd_ADC_readback::
	xcall push_gset3
	mov R10,R16
	sbiw R28,8
	.dbline -1
	.dbline 343
; 
; 
; /*****************************************************************************
; Function:    			dd_ADC_readback
; ==============================================================================
; Description:
; 	Only used for external ADC, voltage, and temperature readback
; *****************************************************************************/
; void dd_ADC_readback(unsigned char R7_value)
; {
	.dbline 346
; 	union ADF70XX_REG_T temp, ADC_readback;
; 
; 	if ( phy_state == PHY_POWERON )
	lds R24,_phy_state
	cpi R24,2
	brne L55
	.dbline 347
; 	{
	.dbline 348
; 		temp.whole_reg = 0x108;					//Enable ADC
	ldi R20,8
	ldi R21,1
	ldi R22,0
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 349
; 		dd_write_7021_reg(&temp.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 351
; 
; 		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
	mov R18,R10
	movw R16,R28
	subi R16,252  ; offset = 4
	sbci R17,255
	xcall _dd_read_7021_reg
	.dbline 352
; 	}
L55:
	.dbline 354
; 
; 	if ( phy_state == PHY_IN_TX_MODE )
	lds R24,_phy_state
	cpi R24,4
	brne L57
	.dbline 355
; 	{
	.dbline 356
; 		temp.whole_reg = 0x118;					//Enable ADC
	ldi R20,24
	ldi R21,1
	ldi R22,0
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 357
; 		dd_write_7021_reg(&temp.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 359
; 
; 		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
	mov R18,R10
	movw R16,R28
	subi R16,252  ; offset = 4
	sbci R17,255
	xcall _dd_read_7021_reg
	.dbline 360
; 	}
L57:
	.dbline 362
; 
; 	if ( phy_state == PHY_IN_RX_MODE )
	lds R24,_phy_state
	cpi R24,3
	brne L59
	.dbline 363
; 	{
	.dbline 364
; 		temp.whole_reg = 0x631E9;			//Turn off AGC
	ldi R20,233
	ldi R21,49
	ldi R22,6
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 365
; 		dd_write_7021_reg(&temp.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 367
; 
; 		temp.whole_reg = 0x108;				//Turn on ADC
	ldi R20,8
	ldi R21,1
	ldi R22,0
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 368
; 		dd_write_7021_reg(&temp.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline 370
; 
; 		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
	mov R18,R10
	movw R16,R28
	subi R16,252  ; offset = 4
	sbci R17,255
	xcall _dd_read_7021_reg
	.dbline 371
; 	}
L59:
	.dbline 373
; 
; 	dd_set_ADF7021_Power_off();
	xcall _dd_set_ADF7021_Power_off
	.dbline 376
; 
; 	
; 	dd_uart_port_tx(&ADC_readback.byte[2], 2);
	ldi R18,2
	movw R16,R28
	subi R16,250  ; offset = 6
	sbci R17,255
	xcall _dd_uart_port_tx
	.dbline -2
	.dbline 378
; 
; }
L54:
	adiw R28,8
	xcall pop_gset3
	.dbline 0 ; func end
	ret
	.dbsym l ADC_readback 4 S[ADF70XX_REG_T]
	.dbsym l temp 0 S[ADF70XX_REG_T]
	.dbsym r R7_value 10 c
	.dbend
	.dbfunc e test_mode _test_mode fV
;     test_value -> y+4
; register_value -> y+0
	.even
_test_mode::
	xcall push_gset2
	sbiw R28,8
	.dbline -1
	.dbline 382
; #endif
; 
; void test_mode(void)
; {
	.dbline 386
; 	union ADF70XX_REG_T test_value,register_value;
; 
; 	//	for ADF7021DB2 864M
;     register_value.whole_reg = 0x000001CC;	//for sync word detect;
	ldi R20,204
	ldi R21,1
	ldi R22,0
	ldi R23,0
	movw R30,R28
	std z+0,R20
	std z+1,R21
	std z+2,R22
	std z+3,R23
	.dbline 387
; 	dd_write_7021_reg(&register_value.byte[0]);
	movw R16,R28
	xcall _dd_write_7021_reg
	.dbline -2
	.dbline 432
;     #if  0
; 	//write R1, turn on VCO
; 	register_value.whole_reg = 0x80535011;
; 	dd_write_7021_reg(&register_value.byte[0]);
;     
; 	//write R3, turn on TX/RX clocks
; 	register_value.whole_reg = 0x2B1734E3;
; 	dd_write_7021_reg(&register_value.byte[0]);
; 
; 	//write R6 here, if fine IF filter cal is wanted
; 
; 
; 	//write R5 to start IF filter cal
; 	register_value.whole_reg = 0x00003155;	//write R5 to start IF filter cal
; 	dd_write_7021_reg(&register_value.byte[0]);
; 	dd_short_delay(5);		//delay 0.2ms
; 
; 	//write R11, configure sync word detect
; 	register_value.whole_reg = 0x091A2B3B;	//sync word = 0x123456;
; 	dd_write_7021_reg(&register_value.byte[0]);
; 
; 	//write R12, start sync word detect
; 	register_value.whole_reg = 0x000001CC;	//for sync word detect;
; 	dd_write_7021_reg(&register_value.byte[0]);
; 
; 	//write R0, turn on PLL
; 	register_value.whole_reg = 0x885d7ef0;
; 	dd_write_7021_reg(&register_value.byte[0]);
; 	dd_short_delay(0);		//delay 40us
; 
; 	//write R4, turn on demodulation
; 	register_value.whole_reg = 0x80139A14;
; 	dd_write_7021_reg(&register_value.byte[0]);
; 
; 	if (is_ADF7021_AFC_ON == TRUE)
; 	{
; 		//write R10, turn AFC on
; 		register_value.whole_reg = 0x3296355A;
; 		dd_write_7021_reg(&register_value.byte[0]);
; 	}
; 
; 	has_set_rx_mode_before = TRUE;
; 	phy_state = PHY_IN_RX_MODE;
;     #endif 
; }
L62:
	adiw R28,8
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym l test_value 4 S[ADF70XX_REG_T]
	.dbsym l register_value 0 S[ADF70XX_REG_T]
	.dbend
	.area bss(ram, con, rel)
	.dbfile D:\icc\examples.avr\230M\dd_adf7021.c
_ADF7021_CE_SIGNAL::
	.blkb 1
	.dbsym e ADF7021_CE_SIGNAL _ADF7021_CE_SIGNAL c