📄 dd_adf7021.s
字号:
.module dd_adf7021.c
.area vector(rom, abs)
.org 40
jmp _dd_spi_i2c_isr
.org 72
jmp _dd_adf7021_sync_isr
.org 44
jmp _UART_RECV_DEAL
.org 52
jmp _UART_SEND_DEAL
.area code(ram, con, rel)
.area lit(rom, con, rel)
_gain_correction::
.byte 172,0
.byte 0,0
.byte 't,'L
.byte 48,0
.byte 0,0
.byte 0,0
.byte 0,0
.byte 0,0
.dbfile D:\icc\examples.avr\230M\dd_adf7021.c
.dbsym e gain_correction _gain_correction A[16:16]kc
.area code(ram, con, rel)
.dbfile D:\icc\examples.avr\230M\dd_adf7021.c
.area text(rom, con, rel)
.dbfile D:\icc\examples.avr\230M\dd_adf7021.c
.dbunion 0 4 ADF70XX_REG_T
.dbfield 0 whole_reg l
.dbfield 0 byte A[4:4]c
.dbend
.dbfunc e dd_read_7021_reg _dd_read_7021_reg fS[ADF70XX_REG_T]
; register_value -> y+0
; i -> R10
; j -> R12
; byte -> R14
; readback_config -> R10
.even
_dd_read_7021_reg::
xcall push_arg4
xcall push_gset5
mov R10,R18
sbiw R28,4
.dbline -1
.dbline 34
; #include "dd.h"
; //#include "api.h"
;
; #if 0
; union ADF70XX_REG_T
; {
; unsigned long whole_reg;
; unsigned char byte[4]; // Warning: Be endian-specific when accessing bytes
;
; };
;
; struct MAC_PACKET_HEADER_T
; {
; unsigned int seq_number;
; unsigned char short_address;
; unsigned char payload_length;
;
; };
; #endif
; unsigned char ADF7021_CE_SIGNAL;
; #pragma data:code
; const unsigned char gain_correction[] =
; { 2*86, 0, 0, 0, 2*58, 2*38, 2*24, 0,
; 0, 0, 0, 0, 0, 0, 0, 0 }; // 7021
; #pragma data:code
;
; /****************************************************************************
; * ADF7021 Control Functions *
; ****************************************************************************/
;
;
;
; union ADF70XX_REG_T dd_read_7021_reg(unsigned char readback_config)
; {
.dbline 42
; union ADF70XX_REG_T register_value;
; unsigned char i, j;
; unsigned char byte;
;
;
; #if 1
; /* Write readback and ADC control value */
; register_value.whole_reg = ((readback_config & 0x1F) << 4);
mov R24,R10
clr R25
andi R24,31
andi R25,0
lsl R24
rol R25
lsl R24
rol R25
lsl R24
rol R25
lsl R24
rol R25
movw R2,R24
clr R4
sbrc R3,7
com R4
clr R5
sbrc R4,7
com R5
movw R30,R28
std z+0,R2
std z+1,R3
std z+2,R4
std z+3,R5
.dbline 43
; register_value.whole_reg |= 7; // Address the readback setup register
ldi R20,7
ldi R21,0
ldi R22,0
ldi R23,0
movw R30,R28
ldd R2,z+0
ldd R3,z+1
ldd R4,z+2
ldd R5,z+3
or R2,R20
or R3,R21
or R4,R22
or R5,R23
movw R30,R28
std z+0,R2
std z+1,R3
std z+2,R4
std z+3,R5
.dbline 45
;
; dd_write_7021_reg((unsigned char *)®ister_value);
movw R16,R28
xcall _dd_write_7021_reg
.dbline 47
;
; register_value.whole_reg = 0;
ldi R20,0
ldi R21,0
ldi R22,0
ldi R23,0
movw R30,R28
std z+0,R20
std z+1,R21
std z+2,R22
std z+3,R23
.dbline 52
; #endif
;
; /* Read back value */
;
; PORTA &= ~(1<<ADF7021_SDATA);
cbi 0x1b,2
.dbline 53
; PORTA &= ~(1<<ADF7021_SCLK);
cbi 0x1b,0
.dbline 54
; PORTA |= 1<<ADF7021_SLE;
sbi 0x1b,3
.dbline 57
;
; //Clock in first bit and discard
; PORTA |= 1<<ADF7021_SCLK;
sbi 0x1b,0
.dbline 58
; byte = 0; // Slight pulse extend
clr R14
.dbline 59
; PORTA &= ~(1<<ADF7021_SCLK);
cbi 0x1b,0
.dbline 63
;
;
; /* Clock in data MSbit first */
; for (i=2; i<=3; i++)
ldi R24,2
mov R10,R24
xjmp L12
L9:
.dbline 64
; {
.dbline 65
; for (j=8; j>0; j--)
ldi R24,8
mov R12,R24
xjmp L16
L13:
.dbline 66
; {
.dbline 67
; PORTA |= 1<<ADF7021_SCLK;
sbi 0x1b,0
.dbline 68
; byte += byte; // left shift 1
add R14,R14
.dbline 69
; PORTA &= ~(1<<ADF7021_SCLK);
cbi 0x1b,0
.dbline 71
;
; if ((PINA&0x02)==0x02) byte |= 1;
in R24,0x19
andi R24,2
cpi R24,2
brne L17
.dbline 71
mov R24,R14
ori R24,1
mov R14,R24
L17:
.dbline 72
L14:
.dbline 65
dec R12
L16:
.dbline 65
clr R2
cp R2,R12
brlo L13
.dbline 74
movw R24,R28
mov R30,R10
clr R31
add R30,R24
adc R31,R25
std z+0,R14
.dbline 76
ldi R16,1
ldi R17,0
ldi R18,0
ldi R19,0
xcall _my_delay
.dbline 78
L10:
.dbline 63
inc R10
L12:
.dbline 63
ldi R24,3
cp R24,R10
brsh L9
.dbline 80
; }
;
; register_value.byte[i] = byte;
;
; my_delay(1); //wait for a bit time
;
; }//for i=2 : 3;
;
; PORTA |= 1<<ADF7021_SCLK;
sbi 0x1b,0
.dbline 81
; PORTA &= ~(1<<ADF7021_SCLK);
cbi 0x1b,0
.dbline 87
;
; /*
; ADF7021_SCLK = 1;
; ADF7021_SCLK = 0;
; */
; PORTA &= ~(1<<ADF7021_SLE);
cbi 0x1b,3
.dbline 90
; // All port lines left low
;
; return register_value;
movw R24,R28
ldd R2,y+14
ldd R3,y+15
ldi R16,4
ldi R17,0
st -y,R3
st -y,R2
st -y,R25
st -y,R24
xcall asgnblk
.dbline -2
L7:
adiw R28,4
xcall pop_gset5
adiw R28,4
.dbline 0 ; func end
ret
.dbsym l register_value 0 S[ADF70XX_REG_T]
.dbsym r i 10 c
.dbsym r j 12 c
.dbsym r byte 14 c
.dbsym r readback_config 10 c
.dbend
.dbfunc e dd_write_7021_reg _dd_write_7021_reg fV
; i -> R20
; j -> R22
; byte -> R10
; reg_bytes -> R16,R17
.even
_dd_write_7021_reg::
xcall push_gset3
.dbline -1
.dbline 97
; }
;
;
;
;
; void dd_write_7021_reg(unsigned char * reg_bytes)
; {
.dbline 101
; signed char i, j;
; unsigned char byte;
;
; PORTA &= ~(1<<ADF7021_SLE);
cbi 0x1b,3
.dbline 102
; PORTA &= ~(1<<ADF7021_SCLK);
cbi 0x1b,0
.dbline 107
;
;
; /* Clock data out MSbit first */
;
; for (i=3; i>=0; i--)
ldi R20,3
xjmp L23
L20:
.dbline 109
;
; {
.dbline 110
; byte = reg_bytes[i];
mov R30,R20
clr R31
sbrc R30,7
com R31
add R30,R16
adc R31,R17
ldd R10,z+0
.dbline 112
;
; for (j=8; j>0; j--)
ldi R22,8
xjmp L27
L24:
.dbline 113
; {
.dbline 114
; PORTA &= ~(1<<ADF7021_SCLK);
cbi 0x1b,0
.dbline 115
; if ((byte & 0x80)==0x80)
mov R24,R10
andi R24,128
cpi R24,128
brne L28
.dbline 116
; {PORTA |= 1<<ADF7021_SDATA;}
.dbline 116
sbi 0x1b,2
.dbline 116
xjmp L29
L28:
.dbline 118
; else
; {PORTA &= ~(1<<ADF7021_SDATA);}
.dbline 118
cbi 0x1b,2
.dbline 118
L29:
.dbline 121
sbi 0x1b,0
.dbline 122
add R10,R10
.dbline 123
L25:
.dbline 112
dec R22
L27:
.dbline 112
clr R2
cp R2,R22
brlt L24
.dbline 124
cbi 0x1b,0
.dbline 125
L21:
.dbline 107
dec R20
L23:
.dbline 107
cpi R20,0
brge L20
.dbline 130
;
;
; PORTA |= 1<<ADF7021_SCLK;
; byte += byte; // left shift 1
; }
; PORTA &= ~(1<<ADF7021_SCLK);
; }
;
;
; /* Strobe the latch */
;
; PORTA |= 1<<ADF7021_SLE;
sbi 0x1b,3
.dbline 131
; PORTA |= 1<<ADF7021_SLE; // Slight pulse extend
sbi 0x1b,3
.dbline 132
; PORTA &= ~(1<<ADF7021_SDATA);
cbi 0x1b,2
.dbline 133
; PORTA &= ~(1<<ADF7021_SLE);
cbi 0x1b,3
.dbline -2
.dbline 137
;
; /* All port lines left low */
;
; }
L19:
xcall pop_gset3
.dbline 0 ; func end
ret
.dbsym r i 20 C
.dbsym r j 22 C
.dbsym r byte 10 c
.dbsym r reg_bytes 16 pc
.dbend
.dbfunc e dd_set_ADF7021_Power_on _dd_set_ADF7021_Power_on fV
.even
_dd_set_ADF7021_Power_on::
.dbline -1
.dbline 141
;
;
; void dd_set_ADF7021_Power_on(void)
; {
.dbline 142
; if (ADF7021_CE_SIGNAL == 0)
lds R2,_ADF7021_CE_SIGNAL
tst R2
brne L31
.dbline 143
; {
.dbline 144
; PORTB |= 1<<ADF7021_CE;
sbi 0x18,3
.dbline 145
; ADF7021_CE_SIGNAL=1;
ldi R24,1
sts _ADF7021_CE_SIGNAL,R24
.dbline 146
; phy_state = PHY_POWERON;
ldi R24,2
sts _phy_state,R24
.dbline 147
; if ( is_use_crystal == TRUE ) dd_short_delay(25); //delay 1ms
lds R24,_is_use_crystal
cpi R24,1
brne L33
.dbline 147
ldi R16,25
xcall _dd_short_delay
L33:
.dbline 148
L31:
.dbline -2
.dbline 149
; }
; }
L30:
.dbline 0 ; func end
ret
.dbend
.dbfunc e dd_set_ADF7021_Power_off _dd_set_ADF7021_Power_off fV
; register_value -> y+0
.even
_dd_set_ADF7021_Power_off::
xcall push_gset2
sbiw R28,4
.dbline -1
.dbline 153
;
;
; void dd_set_ADF7021_Power_off(void)
; {
.dbline 157
; union ADF70XX_REG_T register_value;
;
;
; if ((ADF7021_CE_SIGNAL == 1) && (is_internal_PA_ramp_used == TRUE))
lds R24,_ADF7021_CE_SIGNAL
cpi R24,1
brne L36
lds R24,_is_internal_PA_ramp_used
cpi R24,1
brne L36
.dbline 158
; {
.dbline 159
; register_value.whole_reg = 0x00685502; //Ramp Rate = 16 codes/bit, close PA firstly
ldi R20,2
ldi R21,85
ldi R22,104
ldi R23,0
movw R30,R28
std z+0,R20
std z+1,R21
std z+2,R22
std z+3,R23
.dbline 160
; dd_write_7021_reg(®ister_value.byte[0]);
movw R16,R28
xcall _dd_write_7021_reg
.dbline 161
; dd_short_delay(100); //delay for 4 bits
ldi R16,100
xcall _dd_short_delay
.dbline 162
; }
L36:
.dbline 163
; ADF7021_CE_SIGNAL = 0;
clr R2
sts _ADF7021_CE_SIGNAL,R2
.dbline 164
; PORTB &= ~(1<<ADF7021_CE);
cbi 0x18,3
.dbline 166
;
; has_set_tx_mode_before = FALSE;
sts _has_set_tx_mode_before,R2
.dbline 167
; has_set_rx_mode_before = FALSE;
sts _has_set_rx_mode_before,R2
.dbline 169
;
; phy_state = PHY_DISABLED;
ldi R24,1
sts _phy_state,R24
.dbline -2
.dbline 170
; }
L35:
adiw R28,4
xcall pop_gset2
.dbline 0 ; func end
ret
.dbsym l register_value 0 S[ADF70XX_REG_T]
.dbend
.dbfunc e dd_set_TX_to_RX_mode _dd_set_TX_to_RX_mode fV
; register_value -> y+0
.even
_dd_set_TX_to_RX_mode::
xcall push_gset2
sbiw R28,4
.dbline -1
.dbline 174
;
;
; void dd_set_TX_to_RX_mode(void)
; {
.dbline 178
; union ADF70XX_REG_T register_value;
;
; //write R0, switch TX to RX and change LO
; register_value.whole_reg = 0x885d7ef0;
ldi R20,240
ldi R21,126
ldi R22,93
ldi R23,136
movw R30,R28
std z+0,R20
std z+1,R21
std z+2,R22
std z+3,R23
.dbline 179
; dd_write_7021_reg(®ister_value.byte[0]);
movw R16,R28
xcall _dd_write_7021_reg
.dbline 180
; dd_short_delay(0); //delay 40us
clr R16
xcall _dd_short_delay
.dbline 182
;
; phy_state = PHY_IN_RX_MODE;
ldi R24,3
sts _phy_state,R24
.dbline -2
.dbline 183
; }
L38:
adiw R28,4
xcall pop_gset2
.dbline 0 ; func end
ret
.dbsym l register_value 0 S[ADF70XX_REG_T]
.dbend
.dbfunc e dd_set_TX_mode _dd_set_TX_mode fV
; register_value -> y+0
.even
_dd_set_TX_mode::
xcall push_gset2
sbiw R28,4
.dbline -1
.dbline 186
;
; void dd_set_TX_mode()
; {
.dbline 192
; union ADF70XX_REG_T register_value;
;
; // for ADF7021DB2 864M
;
; //write R1, turn on VCO
; register_value.whole_reg = 0x00535011;
ldi R20,17
ldi R21,80
ldi R22,83
ldi R23,0
movw R30,R28
std z+0,R20
std z+1,R21
std z+2,R22
std z+3,R23
.dbline 193
; dd_write_7021_reg(®ister_value.byte[0]);
movw R16,R28
xcall _dd_write_7021_reg
.dbline 194
; dd_short_delay(20); //delay 800us
ldi R16,20
xcall _dd_short_delay
.dbline 197
;
; //write R3, turn on TX/RX clocks
; register_value.whole_reg = 0x2B1734E3;
ldi R20,227
ldi R21,52
ldi R22,23
ldi R23,43
movw R30,R28
std z+0,R20
std z+1,R21
std z+2,R22
std z+3,R23
.dbline 198
; dd_write_7021_reg(®ister_value.byte[0]);
movw R16,R28
xcall _dd_write_7021_reg
.dbline 201
;
; //write R0, turn on PLL
; register_value.whole_reg = 0x015F3820;
ldi R20,32
ldi R21,56
ldi R22,95
ldi R23,1
movw R30,R28
std z+0,R20
std z+1,R21
std z+2,R22
std z+3,R23
.dbline 202
; dd_write_7021_reg(®ister_value.byte[0]);
movw R16,R28
xcall _dd_write_7021_reg
.dbline 203
; dd_short_delay(0); //delay 40us
clr R16
xcall _dd_short_delay
.dbline 206
;
; //write R2, turn on PA
; register_value.whole_reg = 0x00685582; //Ramp Rate = 16 codes/bit, TX level = 2;
ldi R20,130
ldi R21,85
ldi R22,104
ldi R23,0
movw R30,R28
std z+0,R20
std z+1,R21
std z+2,R22
std z+3,R23
.dbline 208
; // register_value.whole_reg = 0x006FF582; //max power TX
; dd_write_7021_reg(®ister_value.byte[0]);
movw R16,R28
xcall _dd_write_7021_reg
.dbline 209
; if (is_internal_PA_ramp_used == TRUE) dd_short_delay(100); //delay for 4ms, 4 bits for DR = 1Kbps
lds R24,_is_internal_PA_ramp_used
cpi R24,1
brne L40
.dbline 209
ldi R16,100
xcall _dd_short_delay
L40:
.dbline 211
;
; has_set_tx_mode_before = TRUE;
ldi R24,1
sts _has_set_tx_mode_before,R24
.dbline 212
; phy_state = PHY_IN_TX_MODE;
ldi R24,4
sts _phy_state,R24
.dbline -2
.dbline 214
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -