📄 atmega16.lis
字号:
0182 .dbline 211
0182 L21:
0182 .dbline 188
0182 ; while (length-- >0)
0182 1801 movw R2,R16
0184 0150 subi R16,1
0186 1040 sbci R17,0
0188 2220 tst R2
018A 39F7 brne L20
018C 3320 tst R3
018E 29F7 brne L20
0190 X0:
0190 .dbline -2
0190 .dbline 212
0190 ; {
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ; _NOP();
0190 ;
0190 ; }
0190 ; }
0190 L19:
0190 .dbline 0 ; func end
0190 0895 ret
0192 .dbsym r length 16 i
0192 .dbend
0192 .dbfunc e dd_data_port_rx_handler _dd_data_port_rx_handler fV
.even
0192 _dd_data_port_rx_handler::
0192 .dbline -1
0192 .dbline 222
0192 ;
0192 ;
0192 ;
0192 ; /*****************************************************************************
0192 ; Data Functions
0192 ; ****************************************************************************/
0192 ;
0192 ;
0192 ; void dd_data_port_rx_handler(void)
0192 ; {
0192 .dbline 223
0192 ; dd_port_data_tx_frame_idx = 0;
0192 2224 clr R2
0194 20927F00 sts _dd_port_data_tx_frame_idx,R2
0198 .dbline 224
0198 ; dd_port_data_rx_payload_length = 0;
0198 20927D00 sts _dd_port_data_rx_payload_length,R2
019C .dbline 225
019C ; dd_data_port_state = DATA_PORT_IDLE;
019C 81E0 ldi R24,1
019E 80937A00 sts _dd_data_port_state,R24
01A2 .dbline 226
01A2 ; dd_data_packet_phase = PACKET_PHASE_IDLE;
01A2 80937900 sts _dd_data_packet_phase,R24
01A6 .dbline 227
01A6 ; dd_has_received_whole_frame = FALSE;
01A6 20924801 sts _dd_has_received_whole_frame,R2
01AA .dbline -2
01AA .dbline 236
01AA ;
01AA ; //if crc_lo and crc_hi are now both zero, it manifests that data has been received correctly
01AA ; #if 0
01AA ; my_delay(100);
01AA ; SBUF = crc_lo;
01AA ; my_delay(100);
01AA ; SBUF = crc_hi;
01AA ; #endif
01AA ; }
01AA L23:
01AA .dbline 0 ; func end
01AA 0895 ret
01AC .dbend
01AC .dbfunc e dd_uart_port_tx _dd_uart_port_tx fV
01AC ; tx_number -> R18
01AC ; p_buffer -> R16,R17
.even
01AC _dd_uart_port_tx::
01AC .dbline -1
01AC .dbline 244
01AC ;
01AC ;
01AC ;
01AC ; /*****************************************************************************
01AC ; Uart Functions
01AC ; ****************************************************************************/
01AC ; void dd_uart_port_tx(unsigned char * p_buffer, unsigned char tx_number)
01AC ; {
01AC .dbline 246
01AC ;
01AC ; dd_uart_host_state = UART_PORT_TRANSMITTING;
01AC 82E0 ldi R24,2
01AE 80930E00 sts _dd_uart_host_state,R24
01B2 .dbline 248
01B2 ;
01B2 ; uart_tx_payload_length = tx_number;
01B2 20930F00 sts _uart_tx_payload_length,R18
01B6 .dbline 249
01B6 ; uart_buffer_tx_idx = 0;
01B6 2224 clr R2
01B8 20921400 sts _uart_buffer_tx_idx,R2
01BC .dbline 250
01BC ; p_active_uart_buffer = p_buffer;
01BC 10931200 sts _p_active_uart_buffer+1,R17
01C0 00931100 sts _p_active_uart_buffer,R16
01C4 .dbline 251
01C4 ; UDR = p_active_uart_buffer[uart_buffer_tx_idx++];
01C4 3324 clr R3
01C6 822D mov R24,R2
01C8 8F5F subi R24,255 ; addi 1
01CA 80931400 sts _uart_buffer_tx_idx,R24
01CE E22D mov R30,R2
01D0 FF27 clr R31
01D2 E00F add R30,R16
01D4 F11F adc R31,R17
01D6 2080 ldd R2,z+0
01D8 2CB8 out 0xc,R2
01DA .dbline 253
01DA ;
01DA ; SEI();
01DA 7894 sei
01DC .dbline -2
01DC .dbline 255
01DC ;
01DC ; }
01DC L24:
01DC .dbline 0 ; func end
01DC 0895 ret
01DE .dbsym r tx_number 18 c
01DE .dbsym r p_buffer 16 pc
01DE .dbend
.area bss(ram, con, rel)
0000 .dbfile D:\icc\examples.avr\230M\ATMEGA16.c
0000 _crc_hi::
0000 .blkb 1
0001 .dbsym e crc_hi _crc_hi c
0001 _crc_lo::
0001 .blkb 1
0002 .dbsym e crc_lo _crc_lo c
0002 _p_mac_active_tx_frame::
0002 .blkb 2
0004 .dbsym e p_mac_active_tx_frame _p_mac_active_tx_frame pc
0004 _mac_tx_packet_header::
0004 .blkb 4
0008 .dbstruct 0 4 MAC_PACKET_HEADER_T
0008 .dbfield 0 seq_number i
0008 .dbfield 2 short_address c
0008 .dbfield 3 payload_length c
0008 .dbend
0008 .dbsym e mac_tx_packet_header _mac_tx_packet_header S[MAC_PACKET_HEADER_T]
0008 _mac_rx_packet_header::
0008 .blkb 4
000C .dbsym e mac_rx_packet_header _mac_rx_packet_header S[MAC_PACKET_HEADER_T]
000C _phy_state::
000C .blkb 1
000D .dbsym e phy_state _phy_state c
000D _dd_uart_command::
000D .blkb 1
000E .dbsym e dd_uart_command _dd_uart_command c
000E _dd_uart_host_state::
000E .blkb 1
000F .dbsym e dd_uart_host_state _dd_uart_host_state c
000F _uart_tx_payload_length::
000F .blkb 1
0010 .dbsym e uart_tx_payload_length _uart_tx_payload_length c
0010 _uart_rx_payload_length::
0010 .blkb 1
0011 .dbsym e uart_rx_payload_length _uart_rx_payload_length c
0011 _p_active_uart_buffer::
0011 .blkb 2
0013 .dbsym e p_active_uart_buffer _p_active_uart_buffer pc
0013 _uart_buffer_rx_idx::
0013 .blkb 1
0014 .dbsym e uart_buffer_rx_idx _uart_buffer_rx_idx c
0014 _uart_buffer_tx_idx::
0014 .blkb 1
0015 .dbsym e uart_buffer_tx_idx _uart_buffer_tx_idx c
0015 _uart_rx_buffer::
0015 .blkb 100
0079 .dbsym e uart_rx_buffer _uart_rx_buffer A[100:100]c
0079 _dd_data_packet_phase::
0079 .blkb 1
007A .dbsym e dd_data_packet_phase _dd_data_packet_phase c
007A _dd_data_port_state::
007A .blkb 1
007B .dbsym e dd_data_port_state _dd_data_port_state c
007B _p_active_data_tx_buffer::
007B .blkb 2
007D .dbsym e p_active_data_tx_buffer _p_active_data_tx_buffer pc
007D _dd_port_data_rx_payload_length::
007D .blkb 1
007E .dbsym e dd_port_data_rx_payload_length _dd_port_data_rx_payload_length c
007E _dd_port_data_rx_frame_idx::
007E .blkb 1
007F .dbsym e dd_port_data_rx_frame_idx _dd_port_data_rx_frame_idx c
007F _dd_port_data_tx_frame_idx::
007F .blkb 1
0080 .dbsym e dd_port_data_tx_frame_idx _dd_port_data_tx_frame_idx c
0080 _dd_port_data_rx_buffer::
0080 .blkb 100
00E4 .dbsym e dd_port_data_rx_buffer _dd_port_data_rx_buffer A[100:100]c
00E4 _dd_port_data_tx_buffer::
00E4 .blkb 100
0148 .dbsym e dd_port_data_tx_buffer _dd_port_data_tx_buffer A[100:100]c
0148 _dd_has_received_whole_frame::
0148 .blkb 1
0149 .dbsym e dd_has_received_whole_frame _dd_has_received_whole_frame c
0149 _has_set_rx_mode_before::
0149 .blkb 1
014A .dbsym e has_set_rx_mode_before _has_set_rx_mode_before c
014A _has_set_tx_mode_before::
014A .blkb 1
014B .dbsym e has_set_tx_mode_before _has_set_tx_mode_before c
014B _is_internal_PA_ramp_used::
014B .blkb 1
014C .dbsym e is_internal_PA_ramp_used _is_internal_PA_ramp_used c
014C _is_fine_IF_filter_cal::
014C .blkb 1
014D .dbsym e is_fine_IF_filter_cal _is_fine_IF_filter_cal c
014D _is_ADF7021_AFC_ON::
014D .blkb 1
014E .dbsym e is_ADF7021_AFC_ON _is_ADF7021_AFC_ON c
014E _is_use_crystal::
014E .blkb 1
014F .dbsym e is_use_crystal _is_use_crystal c
014F _need_keep_transmitting::
014F .blkb 1
0150 .dbsym e need_keep_transmitting _need_keep_transmitting c
0150 _max_transmit_times::
0150 .blkb 1
0151 .dbsym e max_transmit_times _max_transmit_times c
0151 _dd_user_irq_occurred::
0151 .blkb 1
0152 .dbsym e dd_user_irq_occurred _dd_user_irq_occurred c
0152 _sleep_flag::
0152 .blkb 1
0153 .dbsym e sleep_flag _sleep_flag c
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