📄 dd_isr.lis
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00E4 ; dd_port_data_rx_frame_idx++;
00E4 80910000 lds R24,_dd_port_data_rx_frame_idx
00E8 8F5F subi R24,255 ; addi 1
00EA 80930000 sts _dd_port_data_rx_frame_idx,R24
00EE .dbline 90
00EE 43C0 xjmp L27
00F0 L26:
00F0 .dbline 90
00F0 ; }else {
00F0 .dbline 91
00F0 ; if(dd_port_data_rx_frame_idx==(dd_port_data_rx_payload_length+1)){
00F0 80910000 lds R24,_dd_port_data_rx_payload_length
00F4 8F5F subi R24,255 ; addi 1
00F6 20900000 lds R2,_dd_port_data_rx_frame_idx
00FA 2816 cp R2,R24
00FC 61F4 brne L29
00FE .dbline 91
00FE .dbline 93
00FE ;
00FE ; dd_port_data_rx_buffer[dd_port_data_rx_frame_idx-1]=temp;
00FE 80E0 ldi R24,<_dd_port_data_rx_buffer-1
0100 90E0 ldi R25,>_dd_port_data_rx_buffer-1
0102 E22D mov R30,R2
0104 FF27 clr R31
0106 E80F add R30,R24
0108 F91F adc R31,R25
010A 4083 std z+0,R20
010C .dbline 94
010C ; dd_port_data_rx_frame_idx++;
010C 822D mov R24,R2
010E 8F5F subi R24,255 ; addi 1
0110 80930000 sts _dd_port_data_rx_frame_idx,R24
0114 .dbline 96
0114 ;
0114 ; }
0114 30C0 xjmp L30
0116 L29:
0116 .dbline 97
0116 ; else{
0116 .dbline 98
0116 ; if((temp==crc_hi)&&(dd_port_data_rx_buffer[dd_port_data_rx_frame_idx-1]==crc_lo)){
0116 20900000 lds R2,_crc_hi
011A 4215 cp R20,R2
011C 61F5 brne L32
011E 80E0 ldi R24,<_dd_port_data_rx_buffer-1
0120 90E0 ldi R25,>_dd_port_data_rx_buffer-1
0122 E0910000 lds R30,_dd_port_data_rx_frame_idx
0126 FF27 clr R31
0128 E80F add R30,R24
012A F91F adc R31,R25
012C 2080 ldd R2,z+0
012E 30900000 lds R3,_crc_lo
0132 2314 cp R2,R3
0134 01F5 brne L32
0136 .dbline 98
0136 .dbline 100
0136 ;
0136 ; SPCR &= 0x3f; // Disable SPI,Disable I2C/SPI interrupt
0136 8DB1 in R24,0xd
0138 8F73 andi R24,63
013A 8DB9 out 0xd,R24
013C .dbline 102
013C ; //dd_has_received_whole_frame = TRUE;
013C ; uart_tx_payload_length=dd_port_data_rx_payload_length;
013C 20900000 lds R2,_dd_port_data_rx_payload_length
0140 20920000 sts _uart_tx_payload_length,R2
0144 .dbline 103
0144 ; memcpy(uart_tx_buffer,&dd_port_data_rx_buffer[0], uart_tx_payload_length);
0144 3324 clr R3
0146 3982 std y+1,R3
0148 2882 std y+0,R2
014A 20E0 ldi R18,<_dd_port_data_rx_buffer
014C 30E0 ldi R19,>_dd_port_data_rx_buffer
014E 00E0 ldi R16,<_uart_tx_buffer
0150 10E0 ldi R17,>_uart_tx_buffer
0152 0E940000 xcall _memcpy
0156 .dbline 104
0156 ; uart_buffer_tx_idx=0;
0156 2224 clr R2
0158 20920000 sts _uart_buffer_tx_idx,R2
015C .dbline 105
015C ; UDR = uart_tx_buffer[uart_buffer_tx_idx++];
015C 3324 clr R3
015E 822D mov R24,R2
0160 8F5F subi R24,255 ; addi 1
0162 80930000 sts _uart_buffer_tx_idx,R24
0166 80E0 ldi R24,<_uart_tx_buffer
0168 90E0 ldi R25,>_uart_tx_buffer
016A E22D mov R30,R2
016C FF27 clr R31
016E E80F add R30,R24
0170 F91F adc R31,R25
0172 2080 ldd R2,z+0
0174 2CB8 out 0xc,R2
0176 .dbline 106
0176 ; }
0176 L32:
0176 .dbline 111
0176 ;
0176 ;
0176 ;
0176 ;
0176 ; }
0176 L30:
0176 .dbline 113
0176 ;
0176 ; }
0176 L27:
0176 L25:
0176 .dbline 115
0176 L22:
0176 .dbline -2
0176 .dbline 117
0176 ;
0176 ; }
0176 ;
0176 ; }
0176 L7:
0176 2296 adiw R28,2
0178 0E940000 xcall pop_gset1
017C 0E940000 xcall pop_lset
0180 .dbline 0 ; func end
0180 1895 reti
0182 .dbsym r temp 20 c
0182 .dbend
0182 .dbfunc e dd_adf7021_sync_isr _dd_adf7021_sync_isr fV
0182 ; byte -> <dead>
0182 ; j -> <dead>
0182 ; i -> <dead>
.even
0182 _dd_adf7021_sync_isr::
0182 0E940000 xcall push_lset
0186 .dbline -1
0186 .dbline 124
0186 ;
0186 ;
0186 ; /*****************************************************************************
0186 ; * Function: dd_adf7021_sync_isr
0186 ; ****************************************************************************/
0186 ; void dd_adf7021_sync_isr(void) // 8051 vector 0x0003
0186 ; {
0186 .dbline 127
0186 ;
0186 ; unsigned char i,j,byte;
0186 ; CLI(); // Not needed if we're in an interrupt thread
0186 F894 cli
0188 .dbline 130
0188 ;
0188 ;
0188 ; crc16_reset();
0188 0E940000 xcall _crc16_reset
018C .dbline 132
018C ;
018C ; SPCR |= 0x40; // Enable SPI port now for correct byte sync
018C 6E9A sbi 0xd,6
018E .dbline 134
018E ;
018E ; crc16_reset();
018E 0E940000 xcall _crc16_reset
0192 L36:
0192 .dbline 137
0192 .dbline 138
0192 L37:
0192 .dbline 136
0192 ;
0192 ; while((PINB&0x80)==0x80)
0192 26B2 in R2,0x16
0194 3324 clr R3
0196 27FC sbrc R2,7
0198 FCCF rjmp L36
019A L39:
019A .dbline 140
019A .dbline 141
019A L40:
019A .dbline 139
019A ; {
019A ; }
019A ; while ((PINB&0x80)!=0x80)
019A 86B3 in R24,0x16
019C 8078 andi R24,128
019E 8038 cpi R24,128
01A0 E1F7 brne L39
01A2 .dbline 143
01A2 ; {
01A2 ; }
01A2 ;
01A2 ; SPCR |= 0x80; // Enable I2C/SPI interrupt
01A2 6F9A sbi 0xd,7
01A4 .dbline 146
01A4 ;
01A4 ; //SPDR = 0xFF;
01A4 ; SPSR &= ~0x80; //to avoid the first byte 0x00;
01A4 7798 cbi 0xe,7
01A6 .dbline 148
01A6 ;
01A6 ; dd_data_port_state = DATA_PORT_RECEIVING;
01A6 83E0 ldi R24,3
01A8 80930000 sts _dd_data_port_state,R24
01AC .dbline 149
01AC ; dd_data_packet_phase = PACKET_PHASE_HEADER;
01AC 84E0 ldi R24,4
01AE 80930000 sts _dd_data_packet_phase,R24
01B2 .dbline 150
01B2 ; dd_port_data_rx_frame_idx=0;
01B2 2224 clr R2
01B4 20920000 sts _dd_port_data_rx_frame_idx,R2
01B8 .dbline -2
01B8 .dbline 153
01B8 ;
01B8 ; //P3 ^= 0x10;
01B8 ; }
01B8 L35:
01B8 0E940000 xcall pop_lset
01BC .dbline 0 ; func end
01BC 1895 reti
01BE .dbsym l byte 1 c
01BE .dbsym l j 1 c
01BE .dbsym l i 1 c
01BE .dbend
01BE .dbfunc e UART_RECV_DEAL _UART_RECV_DEAL fV
01BE ; temp -> R16
.even
01BE _UART_RECV_DEAL::
01BE 2A92 st -y,R2
01C0 0A93 st -y,R16
01C2 8A93 st -y,R24
01C4 9A93 st -y,R25
01C6 EA93 st -y,R30
01C8 FA93 st -y,R31
01CA 2FB6 in R2,0x3f
01CC 2A92 st -y,R2
01CE .dbline -1
01CE .dbline 173
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
01CE ;
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