230m.lst

ADI公司射频芯片7020＋ATMEGA16射频模块源程序

(0286) {
(0287) 	union ADF70XX_REG_T uartlog;
(0288) 	uartlog = dd_read_7021_reg(0x10);
    044B E120      LDI	R18,0x10
    044C 018E      MOVW	R16,R28
    044D DE3C      RCALL	_dd_read_7021_reg
(0289) 	dd_uart_port_tx(&uartlog.byte[2], 2);
    044E E022      LDI	R18,2
    044F 018E      MOVW	R16,R28
    0450 5F0E      SUBI	R16,0xFE
    0451 4F1F      SBCI	R17,0xFF
    0452 940E072A  CALL	_dd_uart_port_tx
(0290) }
    0454 9624      ADIW	R28,4
    0455 9508      RET
_dd_read_RSSI:
  RSSI_value           --> Y+2
  rssi                 --> Y+0
    0456 9726      SBIW	R28,6
(0291) 
(0292) 
(0293) 
(0294) 
(0295) 
(0296) void dd_read_RSSI(void)
(0297) {
(0298)     signed int rssi = 0;
    0457 2422      CLR	R2
    0458 2433      CLR	R3
    0459 8239      STD	Y+1,R3
    045A 8228      STD	Y+0,R2
(0299) 	union ADF70XX_REG_T RSSI_value;
(0300) 
(0301) 	RSSI_value = dd_read_7021_reg(0x14);
    045B E124      LDI	R18,0x14
    045C 018E      MOVW	R16,R28
    045D 5F0E      SUBI	R16,0xFE
    045E 4F1F      SBCI	R17,0xFF
    045F DE2A      RCALL	_dd_read_7021_reg
(0302) 
(0303) 	RSSI_value.whole_reg += RSSI_value.whole_reg ;
    0460 01FE      MOVW	R30,R28
    0461 8022      LDD	R2,Z+2
    0462 8033      LDD	R3,Z+3
    0463 8044      LDD	R4,Z+4
    0464 8055      LDD	R5,Z+5
    0465 01FE      MOVW	R30,R28
    0466 8062      LDD	R6,Z+2
    0467 8073      LDD	R7,Z+3
    0468 8084      LDD	R8,Z+4
    0469 8095      LDD	R9,Z+5
    046A 0C62      ADD	R6,R2
    046B 1C73      ADC	R7,R3
    046C 1C84      ADC	R8,R4
    046D 1C95      ADC	R9,R5
    046E 01FE      MOVW	R30,R28
    046F 8262      STD	Z+2,R6
    0470 8273      STD	Z+3,R7
    0471 8284      STD	Z+4,R8
    0472 8295      STD	Z+5,R9
(0304) 
(0305)     rssi = RSSI_value.byte[3];
    0473 802D      LDD	R2,Y+5
    0474 2433      CLR	R3
    0475 8239      STD	Y+1,R3
    0476 8228      STD	Y+0,R2
(0306) 	rssi += gain_correction[RSSI_value.byte[2] & 0x0F] ;
    0477 E584      LDI	R24,0x54
    0478 E092      LDI	R25,2
    0479 81EC      LDD	R30,Y+4
    047A 27FF      CLR	R31
    047B 70EF      ANDI	R30,0xF
    047C 70F0      ANDI	R31,0
    047D 0FE8      ADD	R30,R24
    047E 1FF9      ADC	R31,R25
    047F 9024      LPM	R2,0(Z)
    0480 2433      CLR	R3
    0481 8048      LDD	R4,Y+0
    0482 8059      LDD	R5,Y+1
    0483 0C42      ADD	R4,R2
    0484 1C53      ADC	R5,R3
    0485 8259      STD	Y+1,R5
    0486 8248      STD	Y+0,R4
(0307)     rssi = rssi /4 ;
    0487 E024      LDI	R18,4
    0488 E030      LDI	R19,0
    0489 0182      MOVW	R16,R4
    048A 940E075A  CALL	div16s
    048C 8319      STD	Y+1,R17
    048D 8308      STD	Y+0,R16
(0308) 	//RSSI(dBm) = rssi + 130
(0309) 
(0310) 	dd_uart_port_tx((unsigned char *)&rssi, 2);
    048E E022      LDI	R18,2
    048F 018E      MOVW	R16,R28
    0490 940E072A  CALL	_dd_uart_port_tx
(0311) }
    0492 9626      ADIW	R28,6
    0493 9508      RET
_dd_read_filter_cal:
  uartlog              --> Y+0
    0494 9724      SBIW	R28,4
(0312) 
(0313) 
(0314) 
(0315) void dd_read_filter_cal(void)
(0316) {
(0317) 	union ADF70XX_REG_T uartlog;
(0318) 
(0319) 	//dd_set_ADF7021_Power_on();
(0320) 	uartlog = dd_read_7021_reg(0x18);
    0495 E128      LDI	R18,0x18
    0496 018E      MOVW	R16,R28
    0497 DDF2      RCALL	_dd_read_7021_reg
(0321) 	dd_uart_port_tx(&uartlog.byte[2], 2);
    0498 E022      LDI	R18,2
    0499 018E      MOVW	R16,R28
    049A 5F0E      SUBI	R16,0xFE
    049B 4F1F      SBCI	R17,0xFF
    049C 940E072A  CALL	_dd_uart_port_tx
(0322) }
    049E 9624      ADIW	R28,4
    049F 9508      RET
_dd_read_ADF70XX_version:
  uartlog              --> Y+0
    04A0 9724      SBIW	R28,4
(0323) 
(0324) 
(0325) 
(0326) void dd_read_ADF70XX_version(void)
(0327) {
(0328) 	union ADF70XX_REG_T uartlog;
(0329) 
(0330) 	dd_set_ADF7021_Power_on();
    04A1 DE88      RCALL	_dd_set_ADF7021_Power_on
(0331) 	uartlog = dd_read_7021_reg(0x1C);
    04A2 E12C      LDI	R18,0x1C
    04A3 018E      MOVW	R16,R28
    04A4 DDE5      RCALL	_dd_read_7021_reg
(0332) 	//dd_uart_port_tx(&uartlog.byte[2], 2);
(0333) }
    04A5 9624      ADIW	R28,4
    04A6 9508      RET
_dd_ADC_readback:
  ADC_readback         --> Y+4
  temp                 --> Y+0
  R7_value             --> R10
    04A7 940E07B4  CALL	push_gset3
    04A9 2EA0      MOV	R10,R16
    04AA 9728      SBIW	R28,0x8
(0334) 
(0335) 
(0336) /*****************************************************************************
(0337) Function:    			dd_ADC_readback
(0338) ==============================================================================
(0339) Description:
(0340) 	Only used for external ADC, voltage, and temperature readback
(0341) *****************************************************************************/
(0342) void dd_ADC_readback(unsigned char R7_value)
(0343) {
(0344) 	union ADF70XX_REG_T temp, ADC_readback;
(0345) 
(0346) 	if ( phy_state == PHY_POWERON )
    04AB 918000D7  LDS	R24,_phy_state
    04AD 3082      CPI	R24,2
    04AE F481      BNE	0x04BF
(0347) 	{
(0348) 		temp.whole_reg = 0x108;					//Enable ADC
    04AF E048      LDI	R20,0x8
    04B0 E051      LDI	R21,1
    04B1 E060      LDI	R22,0
    04B2 E070      LDI	R23,0
    04B3 01FE      MOVW	R30,R28
    04B4 8340      STD	Z+0,R20
    04B5 8351      STD	Z+1,R21
    04B6 8362      STD	Z+2,R22
    04B7 8373      STD	Z+3,R23
(0349) 		dd_write_7021_reg(&temp.byte[0]);
    04B8 018E      MOVW	R16,R28
    04B9 DE48      RCALL	_dd_write_7021_reg
(0350) 
(0351) 		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
    04BA 2D2A      MOV	R18,R10
    04BB 018E      MOVW	R16,R28
    04BC 5F0C      SUBI	R16,0xFC
    04BD 4F1F      SBCI	R17,0xFF
    04BE DDCB      RCALL	_dd_read_7021_reg
(0352) 	}
(0353) 
(0354) 	if ( phy_state == PHY_IN_TX_MODE )
    04BF 918000D7  LDS	R24,_phy_state
    04C1 3084      CPI	R24,4
    04C2 F481      BNE	0x04D3
(0355) 	{
(0356) 		temp.whole_reg = 0x118;					//Enable ADC
    04C3 E148      LDI	R20,0x18
    04C4 E051      LDI	R21,1
    04C5 E060      LDI	R22,0
    04C6 E070      LDI	R23,0
    04C7 01FE      MOVW	R30,R28
    04C8 8340      STD	Z+0,R20
    04C9 8351      STD	Z+1,R21
    04CA 8362      STD	Z+2,R22
    04CB 8373      STD	Z+3,R23
(0357) 		dd_write_7021_reg(&temp.byte[0]);
    04CC 018E      MOVW	R16,R28
    04CD DE34      RCALL	_dd_write_7021_reg
(0358) 
(0359) 		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
    04CE 2D2A      MOV	R18,R10
    04CF 018E      MOVW	R16,R28
    04D0 5F0C      SUBI	R16,0xFC
    04D1 4F1F      SBCI	R17,0xFF
    04D2 DDB7      RCALL	_dd_read_7021_reg
(0360) 	}
(0361) 
(0362) 	if ( phy_state == PHY_IN_RX_MODE )
    04D3 918000D7  LDS	R24,_phy_state
    04D5 3083      CPI	R24,3
    04D6 F4D9      BNE	0x04F2
(0363) 	{
(0364) 		temp.whole_reg = 0x631E9;			//Turn off AGC
    04D7 EE49      LDI	R20,0xE9
    04D8 E351      LDI	R21,0x31
    04D9 E066      LDI	R22,6
    04DA E070      LDI	R23,0
    04DB 01FE      MOVW	R30,R28
    04DC 8340      STD	Z+0,R20
    04DD 8351      STD	Z+1,R21
    04DE 8362      STD	Z+2,R22
    04DF 8373      STD	Z+3,R23
(0365) 		dd_write_7021_reg(&temp.byte[0]);
    04E0 018E      MOVW	R16,R28
    04E1 DE20      RCALL	_dd_write_7021_reg
(0366) 
(0367) 		temp.whole_reg = 0x108;				//Turn on ADC
    04E2 E048      LDI	R20,0x8
    04E3 E051      LDI	R21,1
    04E4 E060      LDI	R22,0
    04E5 E070      LDI	R23,0
    04E6 01FE      MOVW	R30,R28
    04E7 8340      STD	Z+0,R20
    04E8 8351      STD	Z+1,R21
    04E9 8362      STD	Z+2,R22
    04EA 8373      STD	Z+3,R23
(0368) 		dd_write_7021_reg(&temp.byte[0]);
    04EB 018E      MOVW	R16,R28
    04EC DE15      RCALL	_dd_write_7021_reg
(0369) 
(0370) 		ADC_readback = dd_read_7021_reg(R7_value);		//readback ADC value
    04ED 2D2A      MOV	R18,R10
    04EE 018E      MOVW	R16,R28
    04EF 5F0C      SUBI	R16,0xFC
    04F0 4F1F      SBCI	R17,0xFF
    04F1 DD98      RCALL	_dd_read_7021_reg
(0371) 	}
(0372) 
(0373) 	dd_set_ADF7021_Power_off();
    04F2 DE4A      RCALL	_dd_set_ADF7021_Power_off
(0374) 
(0375) 	
(0376) 	dd_uart_port_tx(&ADC_readback.byte[2], 2);
    04F3 E022      LDI	R18,2
    04F4 018E      MOVW	R16,R28
    04F5 5F0A      SUBI	R16,0xFA
    04F6 4F1F      SBCI	R17,0xFF
    04F7 940E072A  CALL	_dd_uart_port_tx
(0377) 
(0378) }
    04F9 9628      ADIW	R28,0x8
    04FA 940E0793  CALL	pop_gset3
    04FC 9508      RET
_test_mode:
  test_value           --> Y+4
  register_value       --> Y+0
    04FD 940E07B0  CALL	push_gset2
    04FF 9728      SBIW	R28,0x8
(0379) #endif
(0380) 
(0381) void test_mode(void)
(0382) {
(0383) 	union ADF70XX_REG_T test_value,register_value;
(0384) 
(0385) 	//	for ADF7021DB2 864M
(0386)     register_value.whole_reg = 0x000001CC;	//for sync word detect;
    0500 EC4C      LDI	R20,0xCC
    0501 E051      LDI	R21,1
    0502 E060      LDI	R22,0
    0503 E070      LDI	R23,0
    0504 01FE      MOVW	R30,R28
    0505 8340      STD	Z+0,R20
    0506 8351      STD	Z+1,R21
    0507 8362      STD	Z+2,R22
    0508 8373      STD	Z+3,R23
(0387) 	dd_write_7021_reg(&register_value.byte[0]);
    0509 018E      MOVW	R16,R28
    050A DDF7      RCALL	_dd_write_7021_reg
(0388)     #if  0
(0389) 	//write R1, turn on VCO
(0390) 	register_value.whole_reg = 0x80535011;
(0391) 	dd_write_7021_reg(&register_value.byte[0]);
(0392)     
(0393) 	//write R3, turn on TX/RX clocks
(0394) 	register_value.whole_reg = 0x2B1734E3;
(0395) 	dd_write_7021_reg(&register_value.byte[0]);
(0396) 
(0397) 	//write R6 here, if fine IF filter cal is wanted
(0398) 
(0399) 
(0400) 	//write R5 to start IF filter cal
(0401) 	register_value.whole_reg = 0x00003155;	//write R5 to start IF filter cal
(0402) 	dd_write_7021_reg(&register_value.byte[0]);
(0403) 	dd_short_delay(5);		//delay 0.2ms
(0404) 
(0405) 	//write R11, configure sync word detect
(0406) 	register_value.whole_reg = 0x091A2B3B;	//sync word = 0x123456;
(0407) 	dd_write_7021_reg(&register_value.byte[0]);
(0408) 
(0409) 	//write R12, start sync word detect
(0410) 	register_value.whole_reg = 0x000001CC;	//for sync word detect;
(0411) 	dd_write_7021_reg(&register_value.byte[0]);
(0412) 
(0413) 	//write R0, turn on PLL
(0414) 	register_value.whole_reg = 0x885d7ef0;
(0415) 	dd_write_7021_reg(&register_value.byte[0]);
(0416) 	dd_short_delay(0);		//delay 40us
(0417) 
(0418) 	//write R4, turn on demodulation
(0419) 	register_value.whole_reg = 0x80139A14;
(0420) 	dd_write_7021_reg(&register_value.byte[0]);
(0421) 
(0422) 	if (is_ADF7021_AFC_ON == TRUE)
(0423) 	{
(0424) 		//write R10, turn AFC on
(0425) 		register_value.whole_reg = 0x3296355A;
(0426) 		dd_write_7021_reg(&register_value.byte[0]);
(0427) 	}
(0428) 
(0429) 	has_set_rx_mode_before = TRUE;
(0430) 	phy_state = PHY_IN_RX_MODE;
(0431)     #endif 
(0432) }
    050B 9628      ADIW	R28,0x8
    050C 940E0790  CALL	pop_gset2
    050E 9508      RET
_dd_spi_i2c_isr:
  temp                 --> R20
    050F 940E07C0  CALL	push_lset
    0511 940E0799  CALL	push_gset1
    0513 9722      SBIW	R28,2
FILE: D:\icc\examples.avr\230M\dd_isr.c
(0001) /*****************************************************************************
(0002) *   File:											       dd_isr.c
(0003) *****************************************************************************/
(0004) 
(0005) #include "dd.h"
(0006) //#include "api.h"
(0007) extern unsigned int crc16(unsigned char byte);
(0008) extern void crc16_reset(void);
(0009) unsigned char uart_tx_buffer[max_uart_buffer_size];
(0010) unsigned char time_count;
(0011) unsigned char rf_tx_state[3],crc_tempn[2];
(0012) /*****************************************************************************
(0013)  * Function:    dd_spi_i2c_isr
(0014)  ****************************************************************************/
(0015) void dd_spi_i2c_isr(void)  // 8051 vector 0x003B
(0016) {
(0017) 	unsigned char temp;
(0018) //	UINT16 temp_crc;
(0019) 
(0020)     /* Handle priority processes first: SPIDAT access is extremely critical */
(0021) 
(0022) 
(0023)     	// Handle SPI interrupt 
(0024)         if (dd_data_port_state == DATA_PORT_TRANSMITTING)
    0514 91800145  LDS	R24,_dd_data_port_state
    0516 3082      CPI	R24,2
    0517 F009      BEQ	0x0519
    0518 C044      RJMP	0x055D
(0025)         {   
(0026) 		
(0027) 		    if(dd_port_data_tx_frame_idx<dd_port_data_tx_buffer[8]+9){
    0519 918001B7  LDS	R24,0x1B7
    051B 5F87      SUBI	R24,0xF7
    051C 9020014A  LDS	R2,_dd_port_data_tx_frame_idx
    051E 1628      CP	R2,R24
    051F F4A0      BCC	0x0534
(0028) 			
(0029) 			        
(0030) 			        temp = dd_port_data_tx_buffer[dd_port_data_tx_frame_idx];
    0520 EA8F      LDI	R24,0xAF
    0521 E091      LDI	R25,1
    0522 2DE2      MOV	R30,R2
    0523 27FF      CLR	R31
    0524 0FE8      ADD	R30,R24
    0525 1FF9      ADC	R31,R25
    0526 8140      LDD	R20,Z+0
(0031) 	 				SPDR = temp;
    0527 B94F      OUT	0x0F,R20
(0032) 					if(dd_port_data_tx_frame_idx>8){
    0528 E088      LDI	R24,0x8
    0529 1582      CP	R24,R2
    052A F418      BCC	0x052E
(0033) 					  
(0034) 					crc16(temp);
    052B 2F04      MOV	R16,R20
    052C 940E026B  CALL	_crc16
(0035) 					   
(0036) 					}