📄 230m.lst
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(0142) if (ADF7021_CE_SIGNAL == 0)
_dd_set_ADF7021_Power_on:
032A 90200060 LDS R2,_ADF7021_CE_SIGNAL
032C 2022 TST R2
032D F471 BNE 0x033C
(0143) {
(0144) PORTB |= 1<<ADF7021_CE;
032E 9AC3 SBI 0x18,3
(0145) ADF7021_CE_SIGNAL=1;
032F E081 LDI R24,1
0330 93800060 STS _ADF7021_CE_SIGNAL,R24
(0146) phy_state = PHY_POWERON;
0332 E082 LDI R24,2
0333 938000D7 STS _phy_state,R24
(0147) if ( is_use_crystal == TRUE ) dd_short_delay(25); //delay 1ms
0335 91800219 LDS R24,_is_use_crystal
0337 3081 CPI R24,1
0338 F419 BNE 0x033C
0339 E109 LDI R16,0x19
033A 940E06BB CALL _dd_short_delay
(0148) }
(0149) }
033C 9508 RET
_dd_set_ADF7021_Power_off:
register_value --> Y+0
033D 940E07B0 CALL push_gset2
033F 9724 SBIW R28,4
(0150)
(0151)
(0152) void dd_set_ADF7021_Power_off(void)
(0153) {
(0154) union ADF70XX_REG_T register_value;
(0155)
(0156)
(0157) if ((ADF7021_CE_SIGNAL == 1) && (is_internal_PA_ramp_used == TRUE))
0340 91800060 LDS R24,_ADF7021_CE_SIGNAL
0342 3081 CPI R24,1
0343 F491 BNE 0x0356
0344 91800216 LDS R24,_is_internal_PA_ramp_used
0346 3081 CPI R24,1
0347 F471 BNE 0x0356
(0158) {
(0159) register_value.whole_reg = 0x00685502; //Ramp Rate = 16 codes/bit, close PA firstly
0348 E042 LDI R20,2
0349 E555 LDI R21,0x55
034A E668 LDI R22,0x68
034B E070 LDI R23,0
034C 01FE MOVW R30,R28
034D 8340 STD Z+0,R20
034E 8351 STD Z+1,R21
034F 8362 STD Z+2,R22
0350 8373 STD Z+3,R23
(0160) dd_write_7021_reg(®ister_value.byte[0]);
0351 018E MOVW R16,R28
0352 DFAF RCALL _dd_write_7021_reg
(0161) dd_short_delay(100); //delay for 4 bits
0353 E604 LDI R16,0x64
0354 940E06BB CALL _dd_short_delay
(0162) }
(0163) ADF7021_CE_SIGNAL = 0;
0356 2422 CLR R2
0357 92200060 STS _ADF7021_CE_SIGNAL,R2
(0164) PORTB &= ~(1<<ADF7021_CE);
0359 98C3 CBI 0x18,3
(0165)
(0166) has_set_tx_mode_before = FALSE;
035A 92200215 STS _has_set_tx_mode_before,R2
(0167) has_set_rx_mode_before = FALSE;
035C 92200214 STS _has_set_rx_mode_before,R2
(0168)
(0169) phy_state = PHY_DISABLED;
035E E081 LDI R24,1
035F 938000D7 STS _phy_state,R24
(0170) }
0361 9624 ADIW R28,4
0362 940E0790 CALL pop_gset2
0364 9508 RET
_dd_set_TX_to_RX_mode:
register_value --> Y+0
0365 940E07B0 CALL push_gset2
0367 9724 SBIW R28,4
(0171)
(0172)
(0173) void dd_set_TX_to_RX_mode(void)
(0174) {
(0175) union ADF70XX_REG_T register_value;
(0176)
(0177) //write R0, switch TX to RX and change LO
(0178) register_value.whole_reg = 0x885d7ef0;
0368 EF40 LDI R20,0xF0
0369 E75E LDI R21,0x7E
036A E56D LDI R22,0x5D
036B E878 LDI R23,0x88
036C 01FE MOVW R30,R28
036D 8340 STD Z+0,R20
036E 8351 STD Z+1,R21
036F 8362 STD Z+2,R22
0370 8373 STD Z+3,R23
(0179) dd_write_7021_reg(®ister_value.byte[0]);
0371 018E MOVW R16,R28
0372 DF8F RCALL _dd_write_7021_reg
(0180) dd_short_delay(0); //delay 40us
0373 2700 CLR R16
0374 940E06BB CALL _dd_short_delay
(0181)
(0182) phy_state = PHY_IN_RX_MODE;
0376 E083 LDI R24,3
0377 938000D7 STS _phy_state,R24
(0183) }
0379 9624 ADIW R28,4
037A 940E0790 CALL pop_gset2
037C 9508 RET
_dd_set_TX_mode:
register_value --> Y+0
037D 940E07B0 CALL push_gset2
037F 9724 SBIW R28,4
(0184)
(0185) void dd_set_TX_mode()
(0186) {
(0187) union ADF70XX_REG_T register_value;
(0188)
(0189) // for ADF7021DB2 864M
(0190)
(0191) //write R1, turn on VCO
(0192) register_value.whole_reg = 0x00535011;
0380 E141 LDI R20,0x11
0381 E550 LDI R21,0x50
0382 E563 LDI R22,0x53
0383 E070 LDI R23,0
0384 01FE MOVW R30,R28
0385 8340 STD Z+0,R20
0386 8351 STD Z+1,R21
0387 8362 STD Z+2,R22
0388 8373 STD Z+3,R23
(0193) dd_write_7021_reg(®ister_value.byte[0]);
0389 018E MOVW R16,R28
038A DF77 RCALL _dd_write_7021_reg
(0194) dd_short_delay(20); //delay 800us
038B E104 LDI R16,0x14
038C 940E06BB CALL _dd_short_delay
(0195)
(0196) //write R3, turn on TX/RX clocks
(0197) register_value.whole_reg = 0x2B1734E3;
038E EE43 LDI R20,0xE3
038F E354 LDI R21,0x34
0390 E167 LDI R22,0x17
0391 E27B LDI R23,0x2B
0392 01FE MOVW R30,R28
0393 8340 STD Z+0,R20
0394 8351 STD Z+1,R21
0395 8362 STD Z+2,R22
0396 8373 STD Z+3,R23
(0198) dd_write_7021_reg(®ister_value.byte[0]);
0397 018E MOVW R16,R28
0398 DF69 RCALL _dd_write_7021_reg
(0199)
(0200) //write R0, turn on PLL
(0201) register_value.whole_reg = 0x015F3820;
0399 E240 LDI R20,0x20
039A E358 LDI R21,0x38
039B E56F LDI R22,0x5F
039C E071 LDI R23,1
039D 01FE MOVW R30,R28
039E 8340 STD Z+0,R20
039F 8351 STD Z+1,R21
03A0 8362 STD Z+2,R22
03A1 8373 STD Z+3,R23
(0202) dd_write_7021_reg(®ister_value.byte[0]);
03A2 018E MOVW R16,R28
03A3 DF5E RCALL _dd_write_7021_reg
(0203) dd_short_delay(0); //delay 40us
03A4 2700 CLR R16
03A5 940E06BB CALL _dd_short_delay
(0204)
(0205) //write R2, turn on PA
(0206) register_value.whole_reg = 0x00685582; //Ramp Rate = 16 codes/bit, TX level = 2;
03A7 E842 LDI R20,0x82
03A8 E555 LDI R21,0x55
03A9 E668 LDI R22,0x68
03AA E070 LDI R23,0
03AB 01FE MOVW R30,R28
03AC 8340 STD Z+0,R20
03AD 8351 STD Z+1,R21
03AE 8362 STD Z+2,R22
03AF 8373 STD Z+3,R23
(0207) // register_value.whole_reg = 0x006FF582; //max power TX
(0208) dd_write_7021_reg(®ister_value.byte[0]);
03B0 018E MOVW R16,R28
03B1 DF50 RCALL _dd_write_7021_reg
(0209) if (is_internal_PA_ramp_used == TRUE) dd_short_delay(100); //delay for 4ms, 4 bits for DR = 1Kbps
03B2 91800216 LDS R24,_is_internal_PA_ramp_used
03B4 3081 CPI R24,1
03B5 F419 BNE 0x03B9
03B6 E604 LDI R16,0x64
03B7 940E06BB CALL _dd_short_delay
(0210)
(0211) has_set_tx_mode_before = TRUE;
03B9 E081 LDI R24,1
03BA 93800215 STS _has_set_tx_mode_before,R24
(0212) phy_state = PHY_IN_TX_MODE;
03BC E084 LDI R24,4
03BD 938000D7 STS _phy_state,R24
(0213)
(0214) }
03BF 9624 ADIW R28,4
03C0 940E0790 CALL pop_gset2
03C2 9508 RET
_dd_set_RX_mode:
register_value --> Y+0
03C3 940E07B0 CALL push_gset2
03C5 9724 SBIW R28,4
(0215) void dd_set_RX_mode()
(0216) {
(0217) union ADF70XX_REG_T register_value;
(0218)
(0219) // for ADF7021DB2 864M
(0220)
(0221) //write R1, turn on VCO
(0222) register_value.whole_reg = 0x00535011;
03C6 E141 LDI R20,0x11
03C7 E550 LDI R21,0x50
03C8 E563 LDI R22,0x53
03C9 E070 LDI R23,0
03CA 01FE MOVW R30,R28
03CB 8340 STD Z+0,R20
03CC 8351 STD Z+1,R21
03CD 8362 STD Z+2,R22
03CE 8373 STD Z+3,R23
(0223) dd_write_7021_reg(®ister_value.byte[0]);
03CF 018E MOVW R16,R28
03D0 DF31 RCALL _dd_write_7021_reg
(0224)
(0225) //write R3, turn on TX/RX clocks
(0226) register_value.whole_reg = 0x2B1734E3;
03D1 EE43 LDI R20,0xE3
03D2 E354 LDI R21,0x34
03D3 E167 LDI R22,0x17
03D4 E27B LDI R23,0x2B
03D5 01FE MOVW R30,R28
03D6 8340 STD Z+0,R20
03D7 8351 STD Z+1,R21
03D8 8362 STD Z+2,R22
03D9 8373 STD Z+3,R23
(0227) dd_write_7021_reg(®ister_value.byte[0]);
03DA 018E MOVW R16,R28
03DB DF26 RCALL _dd_write_7021_reg
(0228)
(0229) //write R6 here, if fine IF filter cal is wanted
(0230)
(0231)
(0232) //write R5 to start IF filter cal
(0233) register_value.whole_reg = 0x00003155; //write R5 to start IF filter cal
03DC E545 LDI R20,0x55
03DD E351 LDI R21,0x31
03DE E060 LDI R22,0
03DF E070 LDI R23,0
03E0 01FE MOVW R30,R28
03E1 8340 STD Z+0,R20
03E2 8351 STD Z+1,R21
03E3 8362 STD Z+2,R22
03E4 8373 STD Z+3,R23
(0234) dd_write_7021_reg(®ister_value.byte[0]);
03E5 018E MOVW R16,R28
03E6 DF1B RCALL _dd_write_7021_reg
(0235) dd_short_delay(5); //delay 0.2ms
03E7 E005 LDI R16,5
03E8 940E06BB CALL _dd_short_delay
(0236)
(0237) //write R11, configure sync word detect
(0238) register_value.whole_reg = 0x091A2B3B; //sync word = 0x123456;
03EA E34B LDI R20,0x3B
03EB E25B LDI R21,0x2B
03EC E16A LDI R22,0x1A
03ED E079 LDI R23,0x9
03EE 01FE MOVW R30,R28
03EF 8340 STD Z+0,R20
03F0 8351 STD Z+1,R21
03F1 8362 STD Z+2,R22
03F2 8373 STD Z+3,R23
(0239) dd_write_7021_reg(®ister_value.byte[0]);
03F3 018E MOVW R16,R28
03F4 DF0D RCALL _dd_write_7021_reg
(0240)
(0241) //write R12, start sync word detect
(0242) register_value.whole_reg = 0x0000018C; //for sync word detect;
03F5 E84C LDI R20,0x8C
03F6 E051 LDI R21,1
03F7 E060 LDI R22,0
03F8 E070 LDI R23,0
03F9 01FE MOVW R30,R28
03FA 8340 STD Z+0,R20
03FB 8351 STD Z+1,R21
03FC 8362 STD Z+2,R22
03FD 8373 STD Z+3,R23
(0243) dd_write_7021_reg(®ister_value.byte[0]);
03FE 018E MOVW R16,R28
03FF DF02 RCALL _dd_write_7021_reg
(0244)
(0245) //write R0, turn on PLL
(0246) register_value.whole_reg = 0x095F2DC0;
0400 EC40 LDI R20,0xC0
0401 E25D LDI R21,0x2D
0402 E56F LDI R22,0x5F
0403 E079 LDI R23,0x9
0404 01FE MOVW R30,R28
0405 8340 STD Z+0,R20
0406 8351 STD Z+1,R21
0407 8362 STD Z+2,R22
0408 8373 STD Z+3,R23
(0247) dd_write_7021_reg(®ister_value.byte[0]);
0409 018E MOVW R16,R28
040A DEF7 RCALL _dd_write_7021_reg
(0248) dd_short_delay(0); //delay 40us
040B 2700 CLR R16
040C 940E06BB CALL _dd_short_delay
(0249)
(0250) //write R4, turn on demodulation
(0251) register_value.whole_reg = 0x8016AA14;
040E E144 LDI R20,0x14
040F EA5A LDI R21,0xAA
0410 E166 LDI R22,0x16
0411 E870 LDI R23,0x80
0412 01FE MOVW R30,R28
0413 8340 STD Z+0,R20
0414 8351 STD Z+1,R21
0415 8362 STD Z+2,R22
0416 8373 STD Z+3,R23
(0252) dd_write_7021_reg(®ister_value.byte[0]);
0417 018E MOVW R16,R28
0418 DEE9 RCALL _dd_write_7021_reg
(0253)
(0254) if (is_ADF7021_AFC_ON == TRUE)
0419 91800218 LDS R24,_is_ADF7021_AFC_ON
041B 3081 CPI R24,1
041C F459 BNE 0x0428
(0255) {
(0256) //write R10, turn AFC on
(0257) register_value.whole_reg = 0x3296355A;
041D E54A LDI R20,0x5A
041E E355 LDI R21,0x35
041F E966 LDI R22,0x96
0420 E372 LDI R23,0x32
0421 01FE MOVW R30,R28
0422 8340 STD Z+0,R20
0423 8351 STD Z+1,R21
0424 8362 STD Z+2,R22
0425 8373 STD Z+3,R23
(0258) dd_write_7021_reg(®ister_value.byte[0]);
0426 018E MOVW R16,R28
0427 DEDA RCALL _dd_write_7021_reg
(0259) }
(0260)
(0261) has_set_rx_mode_before = TRUE;
0428 E081 LDI R24,1
0429 93800214 STS _has_set_rx_mode_before,R24
(0262) phy_state = PHY_IN_RX_MODE;
042B E083 LDI R24,3
042C 938000D7 STS _phy_state,R24
(0263)
(0264) }
042E 9624 ADIW R28,4
042F 940E0790 CALL pop_gset2
0431 9508 RET
_dd_set_RX_to_TX_mode:
register_value --> Y+0
0432 940E07B0 CALL push_gset2
0434 9724 SBIW R28,4
(0265)
(0266)
(0267) void dd_set_RX_to_TX_mode()
(0268) {
(0269) union ADF70XX_REG_T register_value;
(0270)
(0271) //write R0, switch RX to TX and change LO
(0272) register_value.whole_reg = 0x805d7ef0;
0435 EF40 LDI R20,0xF0
0436 E75E LDI R21,0x7E
0437 E56D LDI R22,0x5D
0438 E870 LDI R23,0x80
0439 01FE MOVW R30,R28
043A 8340 STD Z+0,R20
043B 8351 STD Z+1,R21
043C 8362 STD Z+2,R22
043D 8373 STD Z+3,R23
(0273) dd_write_7021_reg(®ister_value.byte[0]);
043E 018E MOVW R16,R28
043F DEC2 RCALL _dd_write_7021_reg
(0274) dd_short_delay(0); //delay 40us
0440 2700 CLR R16
0441 940E06BB CALL _dd_short_delay
(0275)
(0276) //please confirm PA level configuration in dd_set_RX_mode(); if it is different, please re-write R2
(0277)
(0278) phy_state = PHY_IN_TX_MODE;
0443 E084 LDI R24,4
0444 938000D7 STS _phy_state,R24
(0279) }
0446 9624 ADIW R28,4
0447 940E0790 CALL pop_gset2
0449 9508 RET
_dd_read_AFC:
uartlog --> Y+0
044A 9724 SBIW R28,4
(0280)
(0281) /****************************************************************************
(0282) * readback functions *
(0283) ***************************************************************************/
(0284) #if 1
(0285) void dd_read_AFC(void)
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