📄 230m.lst
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(0195) Receive a frame including preamble & sync word, payload length,
(0196) payload and CRC
(0197) *****************************************************************************/
(0198) void receive_constant_frame(void)
(0199) {
(0200) CLI();
023D 94F8 BCLR 7
(0201)
(0202) dd_set_ADF7021_Power_on();
023E 940E032A CALL _dd_set_ADF7021_Power_on
(0203) if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE) dd_set_TX_to_RX_mode();
0240 91800214 LDS R24,_has_set_rx_mode_before
0242 3081 CPI R24,1
0243 F419 BNE 0x0247
0244 E061 LDI R22,1
0245 E070 LDI R23,0
0246 C002 RJMP 0x0249
0247 2766 CLR R22
0248 2777 CLR R23
0249 918000D7 LDS R24,_phy_state
024B 3084 CPI R24,4
024C F419 BNE 0x0250
024D E041 LDI R20,1
024E E050 LDI R21,0
024F C002 RJMP 0x0252
0250 2744 CLR R20
0251 2755 CLR R21
0252 011B MOVW R2,R22
0253 2224 AND R2,R20
0254 2235 AND R3,R21
0255 2022 TST R2
0256 F411 BNE 0x0259
0257 2033 TST R3
0258 F019 BEQ 0x025C
0259 940E0365 CALL _dd_set_TX_to_RX_mode
025B C002 RJMP 0x025E
(0204) else dd_set_RX_mode();
025C 940E03C3 CALL _dd_set_RX_mode
(0205)
(0206) GICR|=0x20; // Enable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
025E B78B IN R24,0x3B
025F 6280 ORI R24,0x20
0260 BF8B OUT 0x3B,R24
(0207)
(0208) SEI();
0261 9478 BSET 7
(0209)
(0210) }
0262 940E0790 CALL pop_gset2
0264 9508 RET
(0211)
(0212)
(0213) void crc16_reset(void)
(0214) {
(0215) crc_lo = crc_hi = 0;
_crc16_reset:
0265 2422 CLR R2
0266 922000CB STS _crc_hi,R2
0268 922000CC STS _crc_lo,R2
(0216) }
026A 9508 RET
_crc16:
combination --> R20
byte --> R16
026B 940E0799 CALL push_gset1
(0217)
(0218)
(0219) unsigned int crc16(unsigned char byte)
(0220) {
(0221) unsigned char combination;
(0222)
(0223) // First calculate the combination term
(0224) combination = crc_lo ^ byte;
026D 914000CC LDS R20,_crc_lo
026F 2740 EOR R20,R16
(0225)
(0226) // Now update the CRC register
(0227) crc_lo = crc_hi ^ crc_lut_low[combination];
0270 E584 LDI R24,0x54
0271 E090 LDI R25,0
0272 2FE4 MOV R30,R20
0273 27FF CLR R31
0274 0FE8 ADD R30,R24
0275 1FF9 ADC R31,R25
0276 91E4 LPM R30,0(Z)
0277 902000CB LDS R2,_crc_hi
0279 262E EOR R2,R30
027A 922000CC STS _crc_lo,R2
(0228) crc_hi = crc_lut_high[combination];
027C E584 LDI R24,0x54
027D E091 LDI R25,1
027E 2FE4 MOV R30,R20
027F 27FF CLR R31
0280 0FE8 ADD R30,R24
0281 1FF9 ADC R31,R25
0282 91E4 LPM R30,0(Z)
0283 93E000CB STS _crc_hi,R30
(0229)
(0230) return (crc_hi << 8) | crc_lo;
0285 2F1E MOV R17,R30
0286 2D02 MOV R16,R2
0287 940E079C CALL pop_gset1
0289 9508 RET
_dd_read_7021_reg:
register_value --> Y+0
i --> R10
j --> R12
byte --> R14
readback_config --> R10
028A 940E0751 CALL push_arg4
028C 940E07BC CALL push_gset5
028E 2EA2 MOV R10,R18
028F 9724 SBIW R28,4
FILE: D:\icc\examples.avr\230M\dd_adf7021.c
(0001) #include "dd.h"
(0002) //#include "api.h"
(0003)
(0004) #if 0
(0005) union ADF70XX_REG_T
(0006) {
(0007) unsigned long whole_reg;
(0008) unsigned char byte[4]; // Warning: Be endian-specific when accessing bytes
(0009)
(0010) };
(0011)
(0012) struct MAC_PACKET_HEADER_T
(0013) {
(0014) unsigned int seq_number;
(0015) unsigned char short_address;
(0016) unsigned char payload_length;
(0017)
(0018) };
(0019) #endif
(0020) unsigned char ADF7021_CE_SIGNAL;
(0021) #pragma data:code
(0022) const unsigned char gain_correction[] =
(0023) { 2*86, 0, 0, 0, 2*58, 2*38, 2*24, 0,
(0024) 0, 0, 0, 0, 0, 0, 0, 0 }; // 7021
(0025) #pragma data:code
(0026)
(0027) /****************************************************************************
(0028) * ADF7021 Control Functions *
(0029) ****************************************************************************/
(0030)
(0031)
(0032)
(0033) union ADF70XX_REG_T dd_read_7021_reg(unsigned char readback_config)
(0034) {
(0035) union ADF70XX_REG_T register_value;
(0036) unsigned char i, j;
(0037) unsigned char byte;
(0038)
(0039)
(0040) #if 1
(0041) /* Write readback and ADC control value */
(0042) register_value.whole_reg = ((readback_config & 0x1F) << 4);
0290 2D8A MOV R24,R10
0291 2799 CLR R25
0292 718F ANDI R24,0x1F
0293 7090 ANDI R25,0
0294 0F88 LSL R24
0295 1F99 ROL R25
0296 0F88 LSL R24
0297 1F99 ROL R25
0298 0F88 LSL R24
0299 1F99 ROL R25
029A 0F88 LSL R24
029B 1F99 ROL R25
029C 011C MOVW R2,R24
029D 2444 CLR R4
029E FC37 SBRC R3,7
029F 9440 COM R4
02A0 2455 CLR R5
02A1 FC47 SBRC R4,7
02A2 9450 COM R5
02A3 01FE MOVW R30,R28
02A4 8220 STD Z+0,R2
02A5 8231 STD Z+1,R3
02A6 8242 STD Z+2,R4
02A7 8253 STD Z+3,R5
(0043) register_value.whole_reg |= 7; // Address the readback setup register
02A8 E047 LDI R20,7
02A9 E050 LDI R21,0
02AA E060 LDI R22,0
02AB E070 LDI R23,0
02AC 01FE MOVW R30,R28
02AD 8020 LDD R2,Z+0
02AE 8031 LDD R3,Z+1
02AF 8042 LDD R4,Z+2
02B0 8053 LDD R5,Z+3
02B1 2A24 OR R2,R20
02B2 2A35 OR R3,R21
02B3 2A46 OR R4,R22
02B4 2A57 OR R5,R23
02B5 01FE MOVW R30,R28
02B6 8220 STD Z+0,R2
02B7 8231 STD Z+1,R3
02B8 8242 STD Z+2,R4
02B9 8253 STD Z+3,R5
(0044)
(0045) dd_write_7021_reg((unsigned char *)®ister_value);
02BA 018E MOVW R16,R28
02BB D046 RCALL _dd_write_7021_reg
(0046)
(0047) register_value.whole_reg = 0;
02BC E040 LDI R20,0
02BD E050 LDI R21,0
02BE E060 LDI R22,0
02BF E070 LDI R23,0
02C0 01FE MOVW R30,R28
02C1 8340 STD Z+0,R20
02C2 8351 STD Z+1,R21
02C3 8362 STD Z+2,R22
02C4 8373 STD Z+3,R23
(0048) #endif
(0049)
(0050) /* Read back value */
(0051)
(0052) PORTA &= ~(1<<ADF7021_SDATA);
02C5 98DA CBI 0x1B,2
(0053) PORTA &= ~(1<<ADF7021_SCLK);
02C6 98D8 CBI 0x1B,0
(0054) PORTA |= 1<<ADF7021_SLE;
02C7 9ADB SBI 0x1B,3
(0055)
(0056) //Clock in first bit and discard
(0057) PORTA |= 1<<ADF7021_SCLK;
02C8 9AD8 SBI 0x1B,0
(0058) byte = 0; // Slight pulse extend
02C9 24EE CLR R14
(0059) PORTA &= ~(1<<ADF7021_SCLK);
02CA 98D8 CBI 0x1B,0
(0060)
(0061)
(0062) /* Clock in data MSbit first */
(0063) for (i=2; i<=3; i++)
02CB E082 LDI R24,2
02CC 2EA8 MOV R10,R24
02CD C01E RJMP 0x02EC
(0064) {
(0065) for (j=8; j>0; j--)
02CE E088 LDI R24,0x8
02CF 2EC8 MOV R12,R24
02D0 C00B RJMP 0x02DC
(0066) {
(0067) PORTA |= 1<<ADF7021_SCLK;
02D1 9AD8 SBI 0x1B,0
(0068) byte += byte; // left shift 1
02D2 0CEE LSL R14
(0069) PORTA &= ~(1<<ADF7021_SCLK);
02D3 98D8 CBI 0x1B,0
(0070)
(0071) if ((PINA&0x02)==0x02) byte |= 1;
02D4 B389 IN R24,0x19
02D5 7082 ANDI R24,2
02D6 3082 CPI R24,2
02D7 F419 BNE 0x02DB
02D8 2D8E MOV R24,R14
02D9 6081 ORI R24,1
02DA 2EE8 MOV R14,R24
02DB 94CA DEC R12
02DC 2422 CLR R2
02DD 142C CP R2,R12
02DE F390 BCS 0x02D1
(0072) }
(0073)
(0074) register_value.byte[i] = byte;
02DF 01CE MOVW R24,R28
02E0 2DEA MOV R30,R10
02E1 27FF CLR R31
02E2 0FE8 ADD R30,R24
02E3 1FF9 ADC R31,R25
02E4 82E0 STD Z+0,R14
(0075)
(0076) my_delay(1); //wait for a bit time
02E5 E001 LDI R16,1
02E6 E010 LDI R17,0
02E7 E020 LDI R18,0
02E8 E030 LDI R19,0
02E9 940E06D7 CALL _my_delay
02EB 94A3 INC R10
02EC E083 LDI R24,3
02ED 158A CP R24,R10
02EE F6F8 BCC 0x02CE
(0077)
(0078) }//for i=2 : 3;
(0079)
(0080) PORTA |= 1<<ADF7021_SCLK;
02EF 9AD8 SBI 0x1B,0
(0081) PORTA &= ~(1<<ADF7021_SCLK);
02F0 98D8 CBI 0x1B,0
(0082)
(0083) /*
(0084) ADF7021_SCLK = 1;
(0085) ADF7021_SCLK = 0;
(0086) */
(0087) PORTA &= ~(1<<ADF7021_SLE);
02F1 98DB CBI 0x1B,3
(0088) // All port lines left low
(0089)
(0090) return register_value;
02F2 01CE MOVW R24,R28
02F3 842E LDD R2,Y+14
02F4 843F LDD R3,Y+15
02F5 E004 LDI R16,4
02F6 E010 LDI R17,0
02F7 923A ST R3,-Y
02F8 922A ST R2,-Y
02F9 939A ST R25,-Y
02FA 938A ST R24,-Y
02FB 940E07EE CALL asgnblk
02FD 9624 ADIW R28,4
02FE 940E0796 CALL pop_gset5
0300 9624 ADIW R28,4
0301 9508 RET
_dd_write_7021_reg:
i --> R20
j --> R22
byte --> R10
reg_bytes --> R16
0302 940E07B4 CALL push_gset3
(0091) }
(0092)
(0093)
(0094)
(0095)
(0096) void dd_write_7021_reg(unsigned char * reg_bytes)
(0097) {
(0098) signed char i, j;
(0099) unsigned char byte;
(0100)
(0101) PORTA &= ~(1<<ADF7021_SLE);
0304 98DB CBI 0x1B,3
(0102) PORTA &= ~(1<<ADF7021_SCLK);
0305 98D8 CBI 0x1B,0
(0103)
(0104)
(0105) /* Clock data out MSbit first */
(0106)
(0107) for (i=3; i>=0; i--)
0306 E043 LDI R20,3
0307 C019 RJMP 0x0321
(0108)
(0109) {
(0110) byte = reg_bytes[i];
0308 2FE4 MOV R30,R20
0309 27FF CLR R31
030A FDE7 SBRC R30,7
030B 95F0 COM R31
030C 0FE0 ADD R30,R16
030D 1FF1 ADC R31,R17
030E 80A0 LDD R10,Z+0
(0111)
(0112) for (j=8; j>0; j--)
030F E068 LDI R22,0x8
0310 C00B RJMP 0x031C
(0113) {
(0114) PORTA &= ~(1<<ADF7021_SCLK);
0311 98D8 CBI 0x1B,0
(0115) if ((byte & 0x80)==0x80)
0312 2D8A MOV R24,R10
0313 7880 ANDI R24,0x80
0314 3880 CPI R24,0x80
0315 F411 BNE 0x0318
(0116) {PORTA |= 1<<ADF7021_SDATA;}
0316 9ADA SBI 0x1B,2
0317 C001 RJMP 0x0319
(0117) else
(0118) {PORTA &= ~(1<<ADF7021_SDATA);}
0318 98DA CBI 0x1B,2
(0119)
(0120)
(0121) PORTA |= 1<<ADF7021_SCLK;
0319 9AD8 SBI 0x1B,0
(0122) byte += byte; // left shift 1
031A 0CAA LSL R10
031B 956A DEC R22
031C 2422 CLR R2
031D 1626 CP R2,R22
031E F394 BLT 0x0311
(0123) }
(0124) PORTA &= ~(1<<ADF7021_SCLK);
031F 98D8 CBI 0x1B,0
0320 954A DEC R20
0321 3040 CPI R20,0
0322 F72C BGE 0x0308
(0125) }
(0126)
(0127)
(0128) /* Strobe the latch */
(0129)
(0130) PORTA |= 1<<ADF7021_SLE;
0323 9ADB SBI 0x1B,3
(0131) PORTA |= 1<<ADF7021_SLE; // Slight pulse extend
0324 9ADB SBI 0x1B,3
(0132) PORTA &= ~(1<<ADF7021_SDATA);
0325 98DA CBI 0x1B,2
(0133) PORTA &= ~(1<<ADF7021_SLE);
0326 98DB CBI 0x1B,3
(0134)
(0135) /* All port lines left low */
(0136)
(0137) }
0327 940E0793 CALL pop_gset3
0329 9508 RET
(0138)
(0139)
(0140) void dd_set_ADF7021_Power_on(void)
(0141) {
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