📄 230m.lst
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__start:
__text_start:
0132 E5CF LDI R28,0x5F
0133 E0D4 LDI R29,4
0134 BFCD OUT 0x3D,R28
0135 BFDE OUT 0x3E,R29
0136 51C0 SUBI R28,0x10
0137 40D0 SBCI R29,0
0138 EA0A LDI R16,0xAA
0139 8308 STD Y+0,R16
013A 2400 CLR R0
013B E6E0 LDI R30,0x60
013C E0F0 LDI R31,0
013D E012 LDI R17,2
013E 31EE CPI R30,0x1E
013F 07F1 CPC R31,R17
0140 F011 BEQ 0x0143
0141 9201 ST R0,Z+
0142 CFFB RJMP 0x013E
0143 8300 STD Z+0,R16
0144 E6E4 LDI R30,0x64
0145 E0F2 LDI R31,2
0146 E6A0 LDI R26,0x60
0147 E0B0 LDI R27,0
0148 E012 LDI R17,2
0149 36E4 CPI R30,0x64
014A 07F1 CPC R31,R17
014B F021 BEQ 0x0150
014C 95C8 LPM
014D 9631 ADIW R30,1
014E 920D ST R0,X+
014F CFF9 RJMP 0x0149
0150 940E0153 CALL _main
_exit:
0152 CFFF RJMP _exit
FILE: D:\icc\examples.avr\230M\main.c
(0001)
(0002) #include "dd.h"
(0003) #include "crc16.h"
(0004)
(0005)
(0006)
(0007) //extern void dd_initialise(void);
(0008) //extern void dd_idle(void);
(0009) //extern void receive_constant_frame(void);
(0010) void transmit_constant_frame(void);
(0011) void crc16_reset(void);
(0012) unsigned char uart_rx_rf_tx_count;
(0013) unsigned char temp_count[4];
(0014) unsigned int temp_count1[4];
(0015) unsigned char led_state[2];
(0016) #define tx_never 1
(0017) #define tx_en 1
(0018) void main()
(0019) {
(0020) dd_initialise();
_main:
0153 940E0654 CALL _dd_initialise
(0021) CLI();
0155 94F8 BCLR 7
(0022) dd_read_ADF70XX_version();
0156 940E04A0 CALL _dd_read_ADF70XX_version
(0023) //dd_read_filter_cal();
(0024) // dd_read_RSSI();
(0025) dd_set_ADF7021_Power_off();
0158 940E033D CALL _dd_set_ADF7021_Power_off
(0026)
(0027) dd_set_ADF7021_Power_on();
015A 940E032A CALL _dd_set_ADF7021_Power_on
(0028) //test_mode();
(0029) //if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE) dd_set_TX_to_RX_mode();
(0030) //else dd_set_RX_mode();
(0031) dd_set_RX_mode();
015C 940E03C3 CALL _dd_set_RX_mode
(0032) //dd_read_filter_cal();
(0033) GICR|=0x20; // Enable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
015E B78B IN R24,0x3B
015F 6280 ORI R24,0x20
0160 BF8B OUT 0x3B,R24
(0034) led_state[0]=0;
0161 2422 CLR R2
0162 9220022B STS 0x22B,R2
(0035) led_state[1]=0;
0164 9220022C STS 0x22C,R2
(0036) SEI();
0166 9478 BSET 7
(0037) #if tx_en
(0038) rf_tx_state[0] = 1;
0167 E081 LDI R24,1
0168 938000C8 STS _rf_tx_state,R24
(0039) uart_rx_rf_tx_count=9;
016A E089 LDI R24,0x9
016B 9380021E STS _sleep_flag+1,R24
(0040) #endif
(0041) DDRB &= ~(1<<SPI_MISO);
016D 98BE CBI 0x17,6
(0042) PORTB |= 1<<SPI_MISO;
016E 9AC6 SBI 0x18,6
016F C039 RJMP 0x01A9
(0043) while(1)
(0044) {
(0045)
(0046) if(rf_tx_state[1]==1){
0170 918000C9 LDS R24,_rf_tx_state+1
0172 3081 CPI R24,1
0173 F541 BNE 0x019C
(0047)
(0048) if(rf_tx_state[2]==1){
0174 918000CA LDS R24,_rf_tx_state+2
0176 3081 CPI R24,1
0177 F521 BNE 0x019C
(0049)
(0050) CLI();
0178 94F8 BCLR 7
(0051) dd_set_ADF7021_Power_off();
0179 940E033D CALL _dd_set_ADF7021_Power_off
(0052) temp_count1[0]=0x8ff;
017B EF8F LDI R24,0xFF
017C E098 LDI R25,0x8
017D 93900224 STS 0x224,R25
017F 93800223 STS 0x223,R24
(0053) while(temp_count1[0]-->0)
0181 90200223 LDS R2,0x223
0183 90300224 LDS R3,0x224
0185 01C1 MOVW R24,R2
0186 9701 SBIW R24,1
0187 93900224 STS 0x224,R25
0189 93800223 STS 0x223,R24
018B 2022 TST R2
018C F7A1 BNE 0x0181
018D 2033 TST R3
018E F791 BNE 0x0181
(0054) {
(0055)
(0056) }
(0057) dd_set_ADF7021_Power_on();
018F 940E032A CALL _dd_set_ADF7021_Power_on
(0058) //if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE) dd_set_TX_to_RX_mode();
(0059) //else dd_set_RX_mode();
(0060) dd_set_RX_mode();
0191 940E03C3 CALL _dd_set_RX_mode
(0061) GICR|=0x20; // Enable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
0193 B78B IN R24,0x3B
0194 6280 ORI R24,0x20
0195 BF8B OUT 0x3B,R24
(0062) SEI();
0196 9478 BSET 7
(0063) rf_tx_state[1]=0;
0197 2422 CLR R2
0198 922000C9 STS _rf_tx_state+1,R2
(0064) rf_tx_state[2]=0;
019A 922000CA STS _rf_tx_state+2,R2
(0065) }
(0066) }
(0067)
(0068) if (rf_tx_state[0] == 1){
019C 918000C8 LDS R24,_rf_tx_state
019E 3081 CPI R24,1
019F F449 BNE 0x01A9
(0069)
(0070) dd_idle();
01A0 940E0698 CALL _dd_idle
(0071) transmit_constant_frame();
01A2 D008 RCALL _transmit_constant_frame
(0072)
(0073) #if tx_never
(0074)
(0075) rf_tx_state[1]=0;
01A3 2422 CLR R2
01A4 922000C9 STS _rf_tx_state+1,R2
(0076) rf_tx_state[0] = 1;
01A6 E081 LDI R24,1
01A7 938000C8 STS _rf_tx_state,R24
01A9 CFC6 RJMP 0x0170
(0077) #else
(0078) rf_tx_state[0] = 0;
(0079) rf_tx_state[1] = 1;
(0080) rf_tx_state[2] = 1;
(0081)
(0082) #endif
(0083) //rf_tx_state[2]=0;
(0084) }
(0085)
(0086)
(0087) }
(0088)
(0089) // for(;;) {my_delay(10000); P3 ^= 0x10; }
(0090)
(0091) }
01AA 9508 RET
_transmit_constant_frame:
byte --> Y+1
i --> Y+1
j --> Y+1
delay_count --> R20
01AB 940E07B4 CALL push_gset3
(0092)
(0093)
(0094)
(0095) /*****************************************************************************
(0096) Function: transmit_constant_frame
(0097) ==============================================================================
(0098) Description:
(0099) Transmit a frame including preamble & sync word, payload length,
(0100) payload and CRC
(0101) *****************************************************************************/
(0102) void transmit_constant_frame(void)
(0103) {
(0104) // prepare tx frame header including preamble, sync word, payload length; the following is just an example
(0105)
(0106)
(0107) //mac_tx_packet_header.seq_number = 0x0FF4;
(0108) //mac_tx_packet_header.short_address = 0xAA;
(0109) //mac_tx_packet_header.payload_length = uart_rx_rf_tx_count;
(0110) unsigned int delay_count;
(0111) unsigned char j,i,byte;
(0112) dd_set_ADF7021_Power_off();
01AD 940E033D CALL _dd_set_ADF7021_Power_off
(0113) delay_count=0x8ff;
01AF EF4F LDI R20,0xFF
01B0 E058 LDI R21,0x8
(0114) PORTA |= 1<<RFMD_EN;
01B1 9ADE SBI 0x1B,6
(0115) DDRB |= 1<<SPI_MISO;
01B2 9ABE SBI 0x17,6
(0116) PORTB |= 1<<SPI_MISO;
01B3 9AC6 SBI 0x18,6
(0117) while(delay_count-->0)
01B4 011A MOVW R2,R20
01B5 5041 SUBI R20,1
01B6 4050 SBCI R21,0
01B7 2022 TST R2
01B8 F7D9 BNE 0x01B4
01B9 2033 TST R3
01BA F7C9 BNE 0x01B4
(0118) {
(0119)
(0120) }
(0121)
(0122)
(0123)
(0124) // prepare payload length
(0125) //0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0x12, 0x34, 0x56
(0126) dd_port_data_tx_buffer[0]=0xAA;
01BB EA8A LDI R24,0xAA
01BC 938001AF STS _dd_port_data_tx_buffer,R24
(0127) dd_port_data_tx_buffer[1]=0xAA;
01BE 938001B0 STS _dd_port_data_tx_buffer+1,R24
(0128) dd_port_data_tx_buffer[2]=0xAA;
01C0 938001B1 STS _dd_port_data_tx_buffer+2,R24
(0129) dd_port_data_tx_buffer[3]=0xAA;
01C2 938001B2 STS _dd_port_data_tx_buffer+3,R24
(0130) dd_port_data_tx_buffer[4]=0xAA;
01C4 938001B3 STS 0x1B3,R24
(0131) dd_port_data_tx_buffer[5]=0x12;
01C6 E182 LDI R24,0x12
01C7 938001B4 STS 0x1B4,R24
(0132) dd_port_data_tx_buffer[6]=0x34;
01C9 E384 LDI R24,0x34
01CA 938001B5 STS 0x1B5,R24
(0133) dd_port_data_tx_buffer[7]=0x56;
01CC E586 LDI R24,0x56
01CD 938001B6 STS 0x1B6,R24
(0134) #if tx_never
(0135) dd_port_data_tx_buffer[8]=0x09;
01CF E089 LDI R24,0x9
01D0 938001B7 STS 0x1B7,R24
(0136) dd_port_data_tx_buffer[9]=0x55;
01D2 E585 LDI R24,0x55
01D3 938001B8 STS 0x1B8,R24
(0137) dd_port_data_tx_buffer[10]=0x55;
01D5 938001B9 STS 0x1B9,R24
(0138) dd_port_data_tx_buffer[11]=0x55;
01D7 938001BA STS 0x1BA,R24
(0139) dd_port_data_tx_buffer[12]=0x76;
01D9 E786 LDI R24,0x76
01DA 938001BB STS 0x1BB,R24
(0140) dd_port_data_tx_buffer[13]=0x54;
01DC E584 LDI R24,0x54
01DD 938001BC STS 0x1BC,R24
(0141) dd_port_data_tx_buffer[14]=0x32;
01DF E382 LDI R24,0x32
01E0 938001BD STS 0x1BD,R24
(0142) dd_port_data_tx_buffer[15]=0x07;
01E2 E087 LDI R24,7
01E3 938001BE STS 0x1BE,R24
(0143) dd_port_data_tx_buffer[16]=0x09;
01E5 E089 LDI R24,0x9
01E6 938001BF STS 0x1BF,R24
(0144) dd_port_data_tx_buffer[17]=0x09;
01E8 938001C0 STS 0x1C0,R24
(0145) #else
(0146) dd_port_data_tx_buffer[8]=uart_rx_rf_tx_count;
(0147) memcpy(&dd_port_data_tx_buffer[9], uart_rx_buffer, uart_rx_rf_tx_count);
(0148) #endif
(0149) //memcpy(&dd_port_data_tx_buffer[9], uart_rx_buffer, uart_rx_rf_tx_count);
(0150)
(0151) dd_set_ADF7021_Power_on();
01EA 940E032A CALL _dd_set_ADF7021_Power_on
(0152)
(0153) if (has_set_tx_mode_before == 1 & phy_state == PHY_IN_RX_MODE) dd_set_RX_to_TX_mode();
01EC 91800215 LDS R24,_has_set_tx_mode_before
01EE 3081 CPI R24,1
01EF F421 BNE 0x01F4
01F0 E081 LDI R24,1
01F1 E090 LDI R25,0
01F2 015C MOVW R10,R24
01F3 C002 RJMP 0x01F6
01F4 24AA CLR R10
01F5 24BB CLR R11
01F6 918000D7 LDS R24,_phy_state
01F8 3083 CPI R24,3
01F9 F419 BNE 0x01FD
01FA E061 LDI R22,1
01FB E070 LDI R23,0
01FC C002 RJMP 0x01FF
01FD 2766 CLR R22
01FE 2777 CLR R23
01FF 0115 MOVW R2,R10
0200 2226 AND R2,R22
0201 2237 AND R3,R23
0202 2022 TST R2
0203 F411 BNE 0x0206
0204 2033 TST R3
0205 F019 BEQ 0x0209
0206 940E0432 CALL _dd_set_RX_to_TX_mode
0208 C002 RJMP 0x020B
(0154) else dd_set_TX_mode();
0209 940E037D CALL _dd_set_TX_mode
(0155)
(0156) CLI();
020B 94F8 BCLR 7
(0157)
(0158) dd_data_port_state = DATA_PORT_TRANSMITTING;
020C E082 LDI R24,2
020D 93800145 STS _dd_data_port_state,R24
(0159) dd_data_packet_phase = PACKET_PHASE_PREAMBLE;
020F 93800144 STS _dd_data_packet_phase,R24
(0160) crc16_reset();
0211 D053 RCALL _crc16_reset
(0161)
(0162) SPCR |= 0x80; // Enable I2C/SPI interrupt
0212 9A6F SBI 0x0D,7
(0163)
(0164)
(0165)
(0166)
(0167) /* Enable SPI */
(0168) SPCR |= 0x40;
0213 9A6E SBI 0x0D,6
(0169)
(0170) //p_mac_active_tx_frame = &mac_preamble_syncword[0];
(0171) dd_port_data_tx_frame_idx = 1;
0214 E081 LDI R24,1
0215 9380014A STS _dd_port_data_tx_frame_idx,R24
(0172) //SBUF = p_mac_active_tx_frame[dd_port_data_tx_frame_idx];
(0173) SPDR = dd_port_data_tx_buffer[dd_port_data_tx_frame_idx];
0217 EA8F LDI R24,0xAF
0218 E091 LDI R25,1
0219 91E0014A LDS R30,_dd_port_data_tx_frame_idx
021B 27FF CLR R31
021C 0FE8 ADD R30,R24
021D 1FF9 ADC R31,R25
021E 8020 LDD R2,Z+0
021F B82F OUT 0x0F,R2
(0174) dd_port_data_tx_frame_idx++;
0220 9180014A LDS R24,_dd_port_data_tx_frame_idx
0222 5F8F SUBI R24,0xFF
0223 9380014A STS _dd_port_data_tx_frame_idx,R24
(0175)
(0176) delay_count=0x8ff;
0225 EF4F LDI R20,0xFF
0226 E058 LDI R21,0x8
(0177) while(delay_count-->0)
0227 011A MOVW R2,R20
0228 5041 SUBI R20,1
0229 4050 SBCI R21,0
022A 2022 TST R2
022B F7D9 BNE 0x0227
022C 2033 TST R3
022D F7C9 BNE 0x0227
(0178) {
(0179)
(0180) }
(0181) dd_set_ADF7021_Power_off();
022E 940E033D CALL _dd_set_ADF7021_Power_off
(0182)
(0183) #if tx_never
(0184) my_delay_1(0xffff);
0230 EF0F LDI R16,0xFF
0231 EF1F LDI R17,0xFF
0232 940E0700 CALL _my_delay_1
(0185) uart_rx_rf_tx_count=9;
0234 E089 LDI R24,0x9
0235 9380021E STS _sleep_flag+1,R24
(0186) #endif
(0187)
(0188) SEI();
0237 9478 BSET 7
(0189) }
0238 940E0793 CALL pop_gset3
023A 9508 RET
_receive_constant_frame:
023B 940E07B0 CALL push_gset2
(0190)
(0191) /*****************************************************************************
(0192) Function: receive_constant_frame
(0193) ==============================================================================
(0194) Description:
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