📄 main.lis
字号:
0124 ; dd_port_data_tx_buffer[16]=0x09;
0124 89E0 ldi R24,9
0126 80931000 sts _dd_port_data_tx_buffer+16,R24
012A .dbline 144
012A ; dd_port_data_tx_buffer[17]=0x09;
012A 80931100 sts _dd_port_data_tx_buffer+17,R24
012E .dbline 151
012E ; #else
012E ; dd_port_data_tx_buffer[8]=uart_rx_rf_tx_count;
012E ; memcpy(&dd_port_data_tx_buffer[9], uart_rx_buffer, uart_rx_rf_tx_count);
012E ; #endif
012E ; //memcpy(&dd_port_data_tx_buffer[9], uart_rx_buffer, uart_rx_rf_tx_count);
012E ;
012E ; dd_set_ADF7021_Power_on();
012E 0E940000 xcall _dd_set_ADF7021_Power_on
0132 .dbline 153
0132 ;
0132 ; if (has_set_tx_mode_before == 1 & phy_state == PHY_IN_RX_MODE) dd_set_RX_to_TX_mode();
0132 80910000 lds R24,_has_set_tx_mode_before
0136 8130 cpi R24,1
0138 21F4 brne L49
013A 81E0 ldi R24,1
013C 90E0 ldi R25,0
013E 5C01 movw R10,R24
0140 02C0 xjmp L50
0142 L49:
0142 AA24 clr R10
0144 BB24 clr R11
0146 L50:
0146 80910000 lds R24,_phy_state
014A 8330 cpi R24,3
014C 19F4 brne L51
014E 61E0 ldi R22,1
0150 70E0 ldi R23,0
0152 02C0 xjmp L52
0154 L51:
0154 6627 clr R22
0156 7727 clr R23
0158 L52:
0158 1501 movw R2,R10
015A 2622 and R2,R22
015C 3722 and R3,R23
015E 2220 tst R2
0160 11F4 brne X3
0162 3320 tst R3
0164 19F0 breq L47
0166 X3:
0166 .dbline 153
0166 0E940000 xcall _dd_set_RX_to_TX_mode
016A 02C0 xjmp L48
016C L47:
016C .dbline 154
016C ; else dd_set_TX_mode();
016C 0E940000 xcall _dd_set_TX_mode
0170 L48:
0170 .dbline 156
0170 ;
0170 ; CLI();
0170 F894 cli
0172 .dbline 158
0172 ;
0172 ; dd_data_port_state = DATA_PORT_TRANSMITTING;
0172 82E0 ldi R24,2
0174 80930000 sts _dd_data_port_state,R24
0178 .dbline 159
0178 ; dd_data_packet_phase = PACKET_PHASE_PREAMBLE;
0178 80930000 sts _dd_data_packet_phase,R24
017C .dbline 160
017C ; crc16_reset();
017C 53D0 xcall _crc16_reset
017E .dbline 162
017E ;
017E ; SPCR |= 0x80; // Enable I2C/SPI interrupt
017E 6F9A sbi 0xd,7
0180 .dbline 168
0180 ;
0180 ;
0180 ;
0180 ;
0180 ; /* Enable SPI */
0180 ; SPCR |= 0x40;
0180 6E9A sbi 0xd,6
0182 .dbline 171
0182 ;
0182 ; //p_mac_active_tx_frame = &mac_preamble_syncword[0];
0182 ; dd_port_data_tx_frame_idx = 1;
0182 81E0 ldi R24,1
0184 80930000 sts _dd_port_data_tx_frame_idx,R24
0188 .dbline 173
0188 ; //SBUF = p_mac_active_tx_frame[dd_port_data_tx_frame_idx];
0188 ; SPDR = dd_port_data_tx_buffer[dd_port_data_tx_frame_idx];
0188 80E0 ldi R24,<_dd_port_data_tx_buffer
018A 90E0 ldi R25,>_dd_port_data_tx_buffer
018C E0910000 lds R30,_dd_port_data_tx_frame_idx
0190 FF27 clr R31
0192 E80F add R30,R24
0194 F91F adc R31,R25
0196 2080 ldd R2,z+0
0198 2FB8 out 0xf,R2
019A .dbline 174
019A ; dd_port_data_tx_frame_idx++;
019A 80910000 lds R24,_dd_port_data_tx_frame_idx
019E 8F5F subi R24,255 ; addi 1
01A0 80930000 sts _dd_port_data_tx_frame_idx,R24
01A4 .dbline 176
01A4 ;
01A4 ; delay_count=0x8ff;
01A4 4FEF ldi R20,2303
01A6 58E0 ldi R21,8
01A8 L53:
01A8 .dbline 178
01A8 .dbline 180
01A8 L54:
01A8 .dbline 177
01A8 ; while(delay_count-->0)
01A8 1A01 movw R2,R20
01AA 4150 subi R20,1
01AC 5040 sbci R21,0
01AE 2220 tst R2
01B0 D9F7 brne L53
01B2 3320 tst R3
01B4 C9F7 brne L53
01B6 X4:
01B6 .dbline 181
01B6 ; {
01B6 ;
01B6 ; }
01B6 ; dd_set_ADF7021_Power_off();
01B6 0E940000 xcall _dd_set_ADF7021_Power_off
01BA .dbline 184
01BA ;
01BA ; #if tx_never
01BA ; my_delay_1(0xffff);
01BA 0FEF ldi R16,65535
01BC 1FEF ldi R17,255
01BE 0E940000 xcall _my_delay_1
01C2 .dbline 185
01C2 ; uart_rx_rf_tx_count=9;
01C2 89E0 ldi R24,9
01C4 80930000 sts _uart_rx_rf_tx_count,R24
01C8 .dbline 188
01C8 ; #endif
01C8 ;
01C8 ; SEI();
01C8 7894 sei
01CA .dbline -2
01CA .dbline 189
01CA ; }
01CA L26:
01CA 0E940000 xcall pop_gset3
01CE .dbline 0 ; func end
01CE 0895 ret
01D0 .dbsym l byte 1 c
01D0 .dbsym l i 1 c
01D0 .dbsym l j 1 c
01D0 .dbsym r delay_count 20 i
01D0 .dbend
01D0 .dbfunc e receive_constant_frame _receive_constant_frame fV
.even
01D0 _receive_constant_frame::
01D0 0E940000 xcall push_gset2
01D4 .dbline -1
01D4 .dbline 199
01D4 ;
01D4 ; /*****************************************************************************
01D4 ; Function: receive_constant_frame
01D4 ; ==============================================================================
01D4 ; Description:
01D4 ; Receive a frame including preamble & sync word, payload length,
01D4 ; payload and CRC
01D4 ; *****************************************************************************/
01D4 ; void receive_constant_frame(void)
01D4 ; {
01D4 .dbline 200
01D4 ; CLI();
01D4 F894 cli
01D6 .dbline 202
01D6 ;
01D6 ; dd_set_ADF7021_Power_on();
01D6 0E940000 xcall _dd_set_ADF7021_Power_on
01DA .dbline 203
01DA ; if (has_set_rx_mode_before == 1 & phy_state == PHY_IN_TX_MODE) dd_set_TX_to_RX_mode();
01DA 80910000 lds R24,_has_set_rx_mode_before
01DE 8130 cpi R24,1
01E0 19F4 brne L59
01E2 61E0 ldi R22,1
01E4 70E0 ldi R23,0
01E6 02C0 xjmp L60
01E8 L59:
01E8 6627 clr R22
01EA 7727 clr R23
01EC L60:
01EC 80910000 lds R24,_phy_state
01F0 8430 cpi R24,4
01F2 19F4 brne L61
01F4 41E0 ldi R20,1
01F6 50E0 ldi R21,0
01F8 02C0 xjmp L62
01FA L61:
01FA 4427 clr R20
01FC 5527 clr R21
01FE L62:
01FE 1B01 movw R2,R22
0200 2422 and R2,R20
0202 3522 and R3,R21
0204 2220 tst R2
0206 11F4 brne X5
0208 3320 tst R3
020A 19F0 breq L57
020C X5:
020C .dbline 203
020C 0E940000 xcall _dd_set_TX_to_RX_mode
0210 02C0 xjmp L58
0212 L57:
0212 .dbline 204
0212 ; else dd_set_RX_mode();
0212 0E940000 xcall _dd_set_RX_mode
0216 L58:
0216 .dbline 206
0216 ;
0216 ; GICR|=0x20; // Enable INT0 interrupt (Connecting ADF7021 INT/LOCK Pin)
0216 8BB7 in R24,0x3b
0218 8062 ori R24,32
021A 8BBF out 0x3b,R24
021C .dbline 208
021C ;
021C ; SEI();
021C 7894 sei
021E .dbline -2
021E .dbline 210
021E ;
021E ; }
021E L56:
021E 0E940000 xcall pop_gset2
0222 .dbline 0 ; func end
0222 0895 ret
0224 .dbend
0224 .dbfunc e crc16_reset _crc16_reset fV
.even
0224 _crc16_reset::
0224 .dbline -1
0224 .dbline 214
0224 ;
0224 ;
0224 ; void crc16_reset(void)
0224 ; {
0224 .dbline 215
0224 ; crc_lo = crc_hi = 0;
0224 2224 clr R2
0226 20920000 sts _crc_hi,R2
022A 20920000 sts _crc_lo,R2
022E .dbline -2
022E .dbline 216
022E ; }
022E L63:
022E .dbline 0 ; func end
022E 0895 ret
0230 .dbend
0230 .dbfunc e crc16 _crc16 fi
0230 ; combination -> R20
0230 ; byte -> R16
.even
0230 _crc16::
0230 0E940000 xcall push_gset1
0234 .dbline -1
0234 .dbline 220
0234 ;
0234 ;
0234 ; unsigned int crc16(unsigned char byte)
0234 ; {
0234 .dbline 224
0234 ; unsigned char combination;
0234 ;
0234 ; // First calculate the combination term
0234 ; combination = crc_lo ^ byte;
0234 40910000 lds R20,_crc_lo
0238 4027 eor R20,R16
023A .dbline 227
023A ;
023A ; // Now update the CRC register
023A ; crc_lo = crc_hi ^ crc_lut_low[combination];
023A 80E0 ldi R24,<_crc_lut_low
023C 90E0 ldi R25,>_crc_lut_low
023E E42F mov R30,R20
0240 FF27 clr R31
0242 E80F add R30,R24
0244 F91F adc R31,R25
0246 E491 lpm R30,Z
0248 20900000 lds R2,_crc_hi
024C 2E26 eor R2,R30
024E 20920000 sts _crc_lo,R2
0252 .dbline 228
0252 ; crc_hi = crc_lut_high[combination];
0252 80E0 ldi R24,<_crc_lut_high
0254 90E0 ldi R25,>_crc_lut_high
0256 E42F mov R30,R20
0258 FF27 clr R31
025A E80F add R30,R24
025C F91F adc R31,R25
025E E491 lpm R30,Z
0260 E0930000 sts _crc_hi,R30
0264 .dbline 230
0264 ;
0264 ; return (crc_hi << 8) | crc_lo;
0264 1E2F mov R17,R30
0266 022D mov R16,R2
0268 .dbline -2
0268 L64:
0268 0E940000 xcall pop_gset1
026C .dbline 0 ; func end
026C 0895 ret
026E .dbsym r combination 20 c
026E .dbsym r byte 16 c
026E .dbend
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