📄 cc2500.c
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void halSpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count);
void halSpiReadBurstReg(BYTE addr, BYTE *buffer, BYTE count);
void halSpiWriteReg(BYTE addr, BYTE value);
void halSpiStrobe(BYTE strobe);
BYTE halSpiReadReg(BYTE addr);
BYTE halSpiReadStatus(BYTE addr);
void halRfWriteRfSettings(void);
void halRfSendPacket(BYTE *txBuffer, UINT8 size);
BYTE halRfReceivePacket(BYTE *rxBuffer, UINT8 *length);
extern unsigned char packet_leng;
extern unsigned char tx_count;
unsigned char tmp,tmp1;
#define WRITE_BURST 0x40
#define READ_SINGLE 0x80
#define READ_BURST 0xC0
//=============================================================================
unsigned char SPI_Byte(unsigned char di) {
unsigned char j;
TXBUF0=di;
for(j=0;j<8;j++);
return (RXBUF0);
}
//=============================================================================
unsigned char halSpiReadReg(unsigned char addr) {
unsigned char d;
P3OUT &= ~CSn;
while(P3IN&SO);
addr|=READ_SINGLE;
SPI_Byte(addr);
d=SPI_Byte(0x00);
P3OUT |= CSn;
return d;
}
//==============================================================================
unsigned char halSpiReadStatus(unsigned char addr)
{
unsigned char d;
P3OUT &= ~CSn;
while(P3IN&SO);
addr|=READ_BURST;
//addr |= READ_SINGLE;
SPI_Byte(addr);
d=SPI_Byte(0x00);
P3OUT |= CSn;
return d;
}
//==============================================================================
void halSpiWriteReg(unsigned char addr, unsigned char value)
{
P3OUT &= ~CSn;
while(P3IN&SO);
addr&=0x7F;
SPI_Byte(addr);
SPI_Byte(value);
P3OUT |= CSn;
}
//==============================================================================
void halSpiReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
{
unsigned char j;
P3OUT &= ~CSn;
while(P3IN&SO);
addr|=READ_BURST;
SPI_Byte(addr);
for(j=0;j<count;j++)
{
buffer[j]=SPI_Byte(0x00);
}
P3OUT |= CSn;
}
//==============================================================================
void POWER_UP_RESET_CC2500() {
unsigned char i;
P3OUT |= CSn;
for(i=0;i<5;i++); // In 8MHz 6uS
P3OUT &= ~CSn;
for(i=0;i<5;i++); // In 8MHz 6uS
P3OUT |= CSn;
for(i=0;i<40;i++); // In 8MHz 60uS , need 40uS(Min)
P3OUT &= ~CSn;
SPI_Byte(CC2500_SRES);
while(P3IN&SO);
P3OUT |= CSn;
}
//==============================================================================
void halSpiWriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
{
unsigned char j;
P3OUT &= ~CSn;
while(P3IN&SO);
addr|=WRITE_BURST;
SPI_Byte(addr);
for(j=0;j<count;j++) {
SPI_Byte(buffer[j]);
}
P3OUT |= CSn;
}
//==============================================================================
void halSpiStrobe(unsigned char strobe) {
P3OUT &= ~CSn;
while(P3IN&SO);
SPI_Byte(strobe);
P3OUT |= CSn;
}
//==============================================================================
void InitCC2500(void)
{
POWER_UP_RESET_CC2500();
halRfWriteRfSettings();
halSpiWriteBurstReg(CC2500_PATABLE,paTable,sizeof(paTable));
}
//==============================================================================
void halRfWriteRfSettings(void)//for 250k
{
halSpiWriteReg(CC2500_FSCTRL1, 0x08);
halSpiWriteReg(CC2500_FSCTRL0, 0x00);
halSpiWriteReg(CC2500_FREQ2, 0x10);
halSpiWriteReg(CC2500_FREQ1, 0xa7);
halSpiWriteReg(CC2500_FREQ0, 0x62); // 500k 250k 10k
halSpiWriteReg(CC2500_MDMCFG4, 0xca); // 0e 2d 78
halSpiWriteReg(CC2500_MDMCFG3, 0x83); // 3b 3b 93
halSpiWriteReg(CC2500_MDMCFG2, 0x9b); // f3 83 mach MSK 111
halSpiWriteReg(CC2500_MDMCFG1, 0x22); // FEC enble 0xA2 0x22
halSpiWriteReg(CC2500_MDMCFG0, 0xf8);
halSpiWriteReg(CC2500_CHANNR, 0x00); //CHANNEL=0X10//30
halSpiWriteReg(CC2500_DEVIATN, 0x34); //00 01 44
halSpiWriteReg(CC2500_FREND1, 0x56);
halSpiWriteReg(CC2500_FREND0, 0x10);
halSpiWriteReg(CC2500_MCSM1, 0x30); //0X00>NO CCA; 0X30>CCA
halSpiWriteReg(CC2500_MCSM0, 0x18);
halSpiWriteReg(CC2500_FOCCFG, 0x16);
halSpiWriteReg(CC2500_BSCFG, 0x6C);
halSpiWriteReg(CC2500_AGCCTRL2, 0x43);
halSpiWriteReg(CC2500_AGCCTRL1, 0x40); //cca=0x10
halSpiWriteReg(CC2500_AGCCTRL0, 0x91);
halSpiWriteReg(CC2500_FSCAL3, 0xE9);
halSpiWriteReg(CC2500_FSCAL2, 0x2a);
halSpiWriteReg(CC2500_FSCAL1, 0x00);
halSpiWriteReg(CC2500_FSCAL0, 0x1f);
halSpiWriteReg(CC2500_FSTEST, 0x59);
halSpiWriteReg(CC2500_TEST2, 0x81);
halSpiWriteReg(CC2500_TEST1, 0x35);
halSpiWriteReg(CC2500_TEST0, 0x09);
halSpiWriteReg(CC2500_IOCFG2, 0x47); //CCA=0x09:1=free
halSpiWriteReg(CC2500_IOCFG0, 0x06);
halSpiWriteReg(CC2500_PKTCTRL1, 0x04); //CRC FLUSH,ADRESS CHECK
halSpiWriteReg(CC2500_PKTCTRL0, 0x05); //white data and CRC enble 0x45
halSpiWriteReg(CC2500_ADDR, 0x00); //ADDRESS=01 FOR RECEIVE
halSpiWriteReg(CC2500_PKTLEN, 0xff);
}// halRfWriteRfSettings
/*
halSpiWriteReg(CC2500_FSCTRL1, 0x08);
halSpiWriteReg(CC2500_FSCTRL0, 0x00);
halSpiWriteReg(CC2500_FREQ2, 0x5D);
halSpiWriteReg(CC2500_FREQ1, 0x93);
halSpiWriteReg(CC2500_FREQ0, 0xB1); // 500k 250k 10k
halSpiWriteReg(CC2500_MDMCFG4, 0x2D); // 0e 2d 78
halSpiWriteReg(CC2500_MDMCFG3, 0x3B); // 3b 3b 93
halSpiWriteReg(CC2500_MDMCFG2, 0x73); // f3 83 mach MSK 111
halSpiWriteReg(CC2500_MDMCFG1, 0xa2); // FEC enble 0xA2 0x22
halSpiWriteReg(CC2500_MDMCFG0, 0xF8);
halSpiWriteReg(CC2500_CHANNR, 0x00); //CHANNEL=0X10//30
halSpiWriteReg(CC2500_DEVIATN, 0x01); //00 01 44
halSpiWriteReg(CC2500_FREND1, 0xB6);
halSpiWriteReg(CC2500_FREND0, 0x10);
halSpiWriteReg(CC2500_MCSM1, 0x30); //0X00>NO CCA; 0X30>CCA
halSpiWriteReg(CC2500_MCSM0, 0x08);
halSpiWriteReg(CC2500_FOCCFG, 0x1D);
halSpiWriteReg(CC2500_BSCFG, 0x1C);
halSpiWriteReg(CC2500_AGCCTRL2, 0xC7);
halSpiWriteReg(CC2500_AGCCTRL1, 0x00); //cca=0x10
halSpiWriteReg(CC2500_AGCCTRL0, 0xB2);
halSpiWriteReg(CC2500_FSCAL3, 0xEA);
halSpiWriteReg(CC2500_FSCAL2, 0x0A);
halSpiWriteReg(CC2500_FSCAL0, 0x11);
halSpiWriteReg(CC2500_FSTEST, 0x59);
halSpiWriteReg(CC2500_TEST2, 0x88);
halSpiWriteReg(CC2500_TEST1, 0x31);
halSpiWriteReg(CC2500_TEST0, 0x0B);
halSpiWriteReg(CC2500_IOCFG2, 0x47); //CCA=0x09:1=free
halSpiWriteReg(CC2500_IOCFG0, 0x06);
halSpiWriteReg(CC2500_PKTCTRL1, 0x04); //CRC FLUSH,ADRESS CHECK
halSpiWriteReg(CC2500_PKTCTRL0, 0x05); //white data and CRC enble 0x45
halSpiWriteReg(CC2500_ADDR, 0x00); //ADDRESS=01 FOR RECEIVE
halSpiWriteReg(CC2500_PKTLEN, 0xff);
*/
//==============================================================================
void halRfSendPacket(BYTE *txBuffer, UINT8 size) {
//halSpiWriteReg(CC2500_IOCFG0, 0x29);
// halSpiWriteReg(CC2500_IOCFG2, 0x07);
halSpiWriteBurstReg(CC2500_TXFIFO, txBuffer, size);
halSpiStrobe(CC2500_STX);
// TAR=0xf000; TACTL &= ~TAIFG;
tx_count=0;
while (!(P2IN&GDO0)) if(tx_count>10) break;
tx_count=0;
//TAR=0xf000; TACTL &= ~TAIFG;
while (P2IN&GDO0) if(tx_count>10) break;
//halSpiWriteReg(CC2500_IOCFG0, 0x06);
}// halRfSendPacket
//==============================================================================
BYTE halRfReceivePacket(BYTE *rxBuffer, BYTE *length) {
BYTE status;
BYTE packetLength;
/* halSpiStrobe(CC2500_SRX);
TAR=0xf000; TACTL &= ~TAIFG;
while (!(P2IN&GDO0)) if(TACTL&TAIFG) return 0;
TAR=0xf000; TACTL &= ~TAIFG;
while (P2IN&GDO0) if(TACTL&TAIFG) return 0;*/
tmp = halSpiReadStatus(CC2500_MARCSTATE);
tmp1=tmp;
tmp=tmp1;
_NOP();
Dly1mS(1);
packetLength = halSpiReadReg(CC2500_RXFIFO);
packet_leng=packetLength;
status = halSpiReadStatus(CC2500_PKTSTATUS);
if (packetLength <= *length)
// if(1)
{
packetLength = *length;
halSpiReadBurstReg(CC2500_RXFIFO, rxBuffer, packetLength);
halSpiStrobe(CC2500_SFRX);
return (status & CRC_OK);
} else {
*length = packetLength;
halSpiStrobe(CC2500_SFRX);
return 0;
}
}// halRfReceivePacket
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